65 	u8              muxsel;  member
84 	u32 regval = readl(mux->feedback_reg[mux->muxsel]);  in clkgena_divmux_is_running()
98 	ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);  in clkgena_divmux_enable()
140 	genamux->muxsel = clk_mux_ops.get_parent(mux_hw);  in clkgena_divmux_get_parent()
141 	if ((s8)genamux->muxsel < 0) {  in clkgena_divmux_get_parent()
144 		genamux->muxsel = 0;  in clkgena_divmux_get_parent()
147 	return genamux->muxsel;  in clkgena_divmux_get_parent()
157 	genamux->muxsel = index;  in clkgena_divmux_set_parent()
174 	struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;  in clkgena_divmux_recalc_rate()
185 	struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;  in clkgena_divmux_set_rate()
196 	struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;  in clkgena_divmux_round_rate()