337 static inline unsigned long clkc_readl(unsigned reg)  in clkc_readl()  function
359 	u32 regctrl0 = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_CTRL0 -  in pll_clk_recalc_rate()
361 	u32 regfreq = clkc_readl(clk->regofs);  in pll_clk_recalc_rate()
362 	u32 regssc = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_SSC -  in pll_clk_recalc_rate()
494 	return !!(clkc_readl(reg) & BIT(0));  in dto_clk_is_enabled()
504 	val = clkc_readl(reg) | BIT(0);  in dto_clk_enable()
516 	val = clkc_readl(reg) & ~BIT(0);  in dto_clk_disable()
525 	u32 finc = clkc_readl(clk->inc_offset);  in dto_clk_recalc_rate()
526 …u32 droff = clkc_readl(clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC…  in dto_clk_recalc_rate()
567 	return clkc_readl(clk->src_offset);  in dto_clk_get_parent()
1211 	return !!(clkc_readl(reg) & BIT(clk->bit));  in unit_clk_is_enabled()
1244 		while (!(clkc_readl(SIRFSOC_NOC_CLK_IDLE_STATUS) &  in unit_clk_disable()
1407 	if (clkc_readl(reset->clk_ofs + 8) & (1 << reset->clk_bit)) {  in atlas7_reset_module()