34 	unsigned int div;  member
48 	    | CPG_DIV6_DIV(clock->div - 1);  in cpg_div6_clock_enable()
83 	unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;  in cpg_div6_clock_recalc_rate()  local
85 	return parent_rate / div;  in cpg_div6_clock_recalc_rate()
91 	unsigned int div;  in cpg_div6_clock_calc_div()  local
96 	div = DIV_ROUND_CLOSEST(parent_rate, rate);  in cpg_div6_clock_calc_div()
97 	return clamp_t(unsigned int, div, 1, 64);  in cpg_div6_clock_calc_div()
103 	unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);  in cpg_div6_clock_round_rate()  local
105 	return *parent_rate / div;  in cpg_div6_clock_round_rate()
112 	unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);  in cpg_div6_clock_set_rate()  local
115 	clock->div = div;  in cpg_div6_clock_set_rate()
120 		clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);  in cpg_div6_clock_set_rate()
215 	clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;  in cpg_div6_clock_init()