44 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_enable()  local
47 	val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))  in cpg_div6_clock_enable()
48 	    | CPG_DIV6_DIV(clock->div - 1);  in cpg_div6_clock_enable()
49 	clk_writel(val, clock->reg);  in cpg_div6_clock_enable()
56 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_disable()  local
59 	val = clk_readl(clock->reg);  in cpg_div6_clock_disable()
69 	clk_writel(val, clock->reg);  in cpg_div6_clock_disable()
74 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_is_enabled()  local
76 	return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);  in cpg_div6_clock_is_enabled()
82 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_recalc_rate()  local
83 	unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;  in cpg_div6_clock_recalc_rate()
111 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_set_rate()  local
115 	clock->div = div;  in cpg_div6_clock_set_rate()
117 	val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;  in cpg_div6_clock_set_rate()
120 		clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);  in cpg_div6_clock_set_rate()
127 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_get_parent()  local
131 	if (clock->src_width == 0)  in cpg_div6_clock_get_parent()
134 	hw_index = (clk_readl(clock->reg) >> clock->src_shift) &  in cpg_div6_clock_get_parent()
135 		   (BIT(clock->src_width) - 1);  in cpg_div6_clock_get_parent()
137 		if (clock->parents[i] == hw_index)  in cpg_div6_clock_get_parent()
148 	struct div6_clock *clock = to_div6_clock(hw);  in cpg_div6_clock_set_parent()  local
155 	mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);  in cpg_div6_clock_set_parent()
156 	hw_index = clock->parents[index];  in cpg_div6_clock_set_parent()
158 	clk_writel((clk_readl(clock->reg) & mask) |  in cpg_div6_clock_set_parent()
159 		(hw_index << clock->src_shift), clock->reg);  in cpg_div6_clock_set_parent()
180 	struct div6_clock *clock;  in cpg_div6_clock_init()  local
186 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);  in cpg_div6_clock_init()
187 	if (!clock)  in cpg_div6_clock_init()
197 	clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),  in cpg_div6_clock_init()
208 	clock->reg = of_iomap(np, 0);  in cpg_div6_clock_init()
209 	if (clock->reg == NULL) {  in cpg_div6_clock_init()
215 	clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;  in cpg_div6_clock_init()
231 			clock->parents[valid_parents] = i;  in cpg_div6_clock_init()
239 		clock->src_shift = clock->src_width = 0;  in cpg_div6_clock_init()
243 		clock->src_shift = 6;  in cpg_div6_clock_init()
244 		clock->src_width = 2;  in cpg_div6_clock_init()
248 		clock->src_shift = 12;  in cpg_div6_clock_init()
249 		clock->src_width = 3;  in cpg_div6_clock_init()
264 	clock->hw.init = &init;  in cpg_div6_clock_init()
266 	clk = clk_register(NULL, &clock->hw);  in cpg_div6_clock_init()
279 	if (clock->reg)  in cpg_div6_clock_init()
280 		iounmap(clock->reg);  in cpg_div6_clock_init()
282 	kfree(clock);  in cpg_div6_clock_init()