Lines Matching refs:MUX
310 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
318 MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
542 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
544 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
552 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
560 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
568 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
576 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
582 MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
596 MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0,
614 MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,