Lines Matching refs:DFLAGS
224 #define DFLAGS CLK_DIVIDER_HIWORD_MASK macro
239 RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
242 RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
245 RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
248 RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
251 RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
254 RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
257 RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
260 RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
263 RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
278 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
285 RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
287 RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
291 RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
294 RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
299 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
305 RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
321 RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
330 RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
360 RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
363 RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
381 RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
384 RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
386 RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
390 RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
393 RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
397 RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
400 RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
407 RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
411 RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
414 RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
423 RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
426 RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
429 RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
432 RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
439 RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
442 RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
444 RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
448 RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
452 RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
455 RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
458 RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
468 RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
471 RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
474 RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
478 RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
481 RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
484 RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
487 RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
503 RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
506 RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
519 RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
523 RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
530 RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
533 RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
537 RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
547 RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
555 RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
563 RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
571 RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
580 RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
594 RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
613 RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),