67 	u32 cfg;  in clk_rcg2_get_parent()  local
70 	ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_get_parent()
74 	cfg &= CFG_SRC_SEL_MASK;  in clk_rcg2_get_parent()
75 	cfg >>= CFG_SRC_SEL_SHIFT;  in clk_rcg2_get_parent()
78 		if (cfg == rcg->parent_map[i].cfg)  in clk_rcg2_get_parent()
117 	u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in clk_rcg2_set_parent()  local
120 				 CFG_SRC_SEL_MASK, cfg);  in clk_rcg2_set_parent()
156 	u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;  in clk_rcg2_recalc_rate()  local
158 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_recalc_rate()
168 		mode = cfg & CFG_MODE_MASK;  in clk_rcg2_recalc_rate()
173 	hid_div = cfg >> CFG_SRC_DIV_SHIFT;  in clk_rcg2_recalc_rate()
229 	u32 cfg, mask;  in clk_rcg2_configure()  local
256 	cfg = f->pre_div << CFG_SRC_DIV_SHIFT;  in clk_rcg2_configure()
257 	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in clk_rcg2_configure()
259 		cfg |= CFG_MODE_DUAL_EDGE;  in clk_rcg2_configure()
261 			rcg->cmd_rcgr + CFG_REG, mask, cfg);  in clk_rcg2_configure()
598 	u32 cfg;  in clk_byte2_set_rate()  local
605 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_byte2_set_rate()
606 	cfg &= CFG_SRC_SEL_MASK;  in clk_byte2_set_rate()
607 	cfg >>= CFG_SRC_SEL_SHIFT;  in clk_byte2_set_rate()
610 		if (cfg == rcg->parent_map[i].cfg) {  in clk_byte2_set_rate()
677 	u32 hid_div, cfg;  in clk_pixel_set_rate()  local
680 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_pixel_set_rate()
681 	cfg &= CFG_SRC_SEL_MASK;  in clk_pixel_set_rate()
682 	cfg >>= CFG_SRC_SEL_SHIFT;  in clk_pixel_set_rate()
685 		if (cfg == rcg->parent_map[i].cfg) {  in clk_pixel_set_rate()