52 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_get_parent()
81 	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_get_parent()
87 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_get_parent()
107 	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_set_parent()
109 	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);  in clk_rcg_set_parent()
221 	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in configure_bank()
228 	ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);  in configure_bank()
237 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
241 		ret = regmap_read(rcg->clkr.regmap, md_reg, &md);  in configure_bank()
245 		ret = regmap_write(rcg->clkr.regmap, md_reg, md);  in configure_bank()
249 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
256 			ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
261 			ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,  in configure_bank()
268 		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
283 	ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);  in configure_bank()
288 		ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in configure_bank()
292 		ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);  in configure_bank()
308 	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_set_parent()
311 	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_set_parent()
314 		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);  in clk_dyn_rcg_set_parent()
356 	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_recalc_rate()
360 		regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);  in clk_rcg_recalc_rate()
365 			regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);  in clk_rcg_recalc_rate()
384 	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_recalc_rate()
387 	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_recalc_rate()
392 		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);  in clk_dyn_rcg_recalc_rate()
460 	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);  in clk_dyn_rcg_determine_rate()
496 		regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);  in __clk_rcg_set_rate()
498 		regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);  in __clk_rcg_set_rate()
500 		regmap_write(rcg->clkr.regmap, rcg->md_reg, md);  in __clk_rcg_set_rate()
502 		regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in __clk_rcg_set_rate()
505 			regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);  in __clk_rcg_set_rate()
507 			regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);  in __clk_rcg_set_rate()
513 		regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in __clk_rcg_set_rate()
517 	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);  in __clk_rcg_set_rate()
519 	regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);  in __clk_rcg_set_rate()
565 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_bypass2_set_rate()
636 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_pixel_set_rate()
710 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);  in clk_rcg_esc_set_rate()
763 	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);  in clk_rcg_lcc_set_rate()
767 		regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);  in clk_rcg_lcc_set_rate()
778 	return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);  in clk_rcg_lcc_enable()
787 	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);  in clk_rcg_lcc_disable()