66 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)  in reg_to_bank()  argument
68 	bank &= BIT(rcg->mux_sel_bit);  in reg_to_bank()
69 	return !!bank;  in reg_to_bank()
77 	int bank;  in clk_dyn_rcg_get_parent()  local
84 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_get_parent()
85 	s = &rcg->s[bank];  in clk_dyn_rcg_get_parent()
87 	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_get_parent()
209 	int bank, new_bank, ret, index;  in configure_bank()  local
224 	bank = reg_to_bank(rcg, reg);  in configure_bank()
225 	new_bank = enabled ? !bank : bank;  in configure_bank()
303 	int bank;  in clk_dyn_rcg_set_parent()  local
309 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_set_parent()
311 	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_set_parent()
314 		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);  in clk_dyn_rcg_set_parent()
315 		f.m = md_to_m(&rcg->mn[bank], md);  in clk_dyn_rcg_set_parent()
316 		f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);  in clk_dyn_rcg_set_parent()
320 		f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;  in clk_dyn_rcg_set_parent()
322 	f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);  in clk_dyn_rcg_set_parent()
379 	int bank;  in clk_dyn_rcg_recalc_rate()  local
385 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_recalc_rate()
387 	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);  in clk_dyn_rcg_recalc_rate()
391 		mn = &rcg->mn[bank];  in clk_dyn_rcg_recalc_rate()
392 		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);  in clk_dyn_rcg_recalc_rate()
402 		pre_div = ns_to_pre_div(&rcg->p[bank], ns);  in clk_dyn_rcg_recalc_rate()
457 	int bank;  in clk_dyn_rcg_determine_rate()  local
461 	bank = reg_to_bank(rcg, reg);  in clk_dyn_rcg_determine_rate()
462 	s = &rcg->s[bank];  in clk_dyn_rcg_determine_rate()