Lines Matching refs:ARRAY_SIZE
75 ARRAY_SIZE(fixed_rate_clks)); in pxa1928_pll_init()
78 ARRAY_SIZE(fixed_factor_clks)); in pxa1928_pll_init()
84 ARRAY_SIZE(uart_factor_tbl), NULL); in pxa1928_pll_init()
100 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
101 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
102 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
103 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
104 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S…
105 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S…
136 ARRAY_SIZE(apbc_mux_clks)); in pxa1928_apb_periph_clk_init()
139 ARRAY_SIZE(apbc_gate_clks)); in pxa1928_apb_periph_clk_init()
152 …{0, "sdh_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SD…
175 ARRAY_SIZE(apmu_mux_clks)); in pxa1928_axi_periph_clk_init()
178 ARRAY_SIZE(apmu_div_clks)); in pxa1928_axi_periph_clk_init()
181 ARRAY_SIZE(apmu_gate_clks)); in pxa1928_axi_periph_clk_init()
190 nr_resets = ARRAY_SIZE(apbc_gate_clks); in pxa1928_clk_reset_init()