Lines Matching refs:ARRAY_SIZE
112 ARRAY_SIZE(fixed_rate_clks)); in mmp2_pll_init()
115 ARRAY_SIZE(fixed_factor_clks)); in mmp2_pll_init()
121 ARRAY_SIZE(uart_factor_tbl), NULL); in mmp2_pll_init()
142 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
143 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
144 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
145 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3…
146 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
147 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
148 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
149 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
150 …{0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIM…
184 ARRAY_SIZE(apbc_mux_clks)); in mmp2_apb_periph_clk_init()
187 ARRAY_SIZE(apbc_gate_clks)); in mmp2_apb_periph_clk_init()
213 …{MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_P…
214 …{MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_P…
251 ARRAY_SIZE(sdh_parent_names), in mmp2_axi_periph_clk_init()
257 ARRAY_SIZE(ccic_parent_names), in mmp2_axi_periph_clk_init()
264 ARRAY_SIZE(ccic_parent_names), in mmp2_axi_periph_clk_init()
270 ARRAY_SIZE(apmu_mux_clks)); in mmp2_axi_periph_clk_init()
273 ARRAY_SIZE(apmu_div_clks)); in mmp2_axi_periph_clk_init()
276 ARRAY_SIZE(apmu_gate_clks)); in mmp2_axi_periph_clk_init()
285 nr_resets = ARRAY_SIZE(apbc_gate_clks); in mmp2_clk_reset_init()