82 	void __iomem *apmu_base;  in mmp2_clk_init()  local
91 	apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);  in mmp2_clk_init()
92 	if (apmu_base == NULL) {  in mmp2_clk_init()
336 				apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);  in mmp2_clk_init()
340 				CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,  in mmp2_clk_init()
344 	clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,  in mmp2_clk_init()
348 	clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,  in mmp2_clk_init()
352 	clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,  in mmp2_clk_init()
356 	clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,  in mmp2_clk_init()
360 	clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,  in mmp2_clk_init()
367 				apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
371 				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,  in mmp2_clk_init()
376 				apmu_base + APMU_DISP0, 0x1b, &clk_lock);  in mmp2_clk_init()
380 				apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);  in mmp2_clk_init()
384 				apmu_base + APMU_DISP0, 0x1024, &clk_lock);  in mmp2_clk_init()
390 				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
394 				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,  in mmp2_clk_init()
399 				apmu_base + APMU_DISP1, 0x1b, &clk_lock);  in mmp2_clk_init()
403 				apmu_base + APMU_CCIC0, 0x1800, &clk_lock);  in mmp2_clk_init()
409 				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
413 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,  in mmp2_clk_init()
418 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);  in mmp2_clk_init()
422 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);  in mmp2_clk_init()
426 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,  in mmp2_clk_init()
431 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);  in mmp2_clk_init()
437 				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);  in mmp2_clk_init()
441 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,  in mmp2_clk_init()
446 				apmu_base + APMU_CCIC1, 0x1b, &clk_lock);  in mmp2_clk_init()
450 				apmu_base + APMU_CCIC1, 0x24, &clk_lock);  in mmp2_clk_init()
454 				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,  in mmp2_clk_init()
459 				apmu_base + APMU_CCIC1, 0x300, &clk_lock);  in mmp2_clk_init()