clk-pll.c - OpenGrok cross reference for /linux-4.4.14/drivers/clk/mediatek/clk-pll.c

Lines Matching refs:REG_CON0

24 #define REG_CON0		0  macro
63 	return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;  in mtk_pll_is_prepared()
96 	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;  in mtk_pll_set_rate_regs()
226 	r = readl(pll->base_addr + REG_CON0);  in mtk_pll_prepare()
228 	writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
238 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_prepare()
240 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_prepare()
252 		r = readl(pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
254 		writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
262 	r = readl(pll->base_addr + REG_CON0);  in mtk_pll_unprepare()
264 	writel(r, pll->base_addr + REG_CON0);  in mtk_pll_unprepare()