78 ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)  in ingenic_pll_recalc_rate()  argument
107 		return parent_rate;  in ingenic_pll_recalc_rate()
119 	return div_u64((u64)parent_rate * m, n * od);  in ingenic_pll_recalc_rate()
124 		 unsigned long rate, unsigned long parent_rate,  in ingenic_pll_calc()  argument
137 	n = parent_rate / (10 * MHZ);  in ingenic_pll_calc()
141 	m = (rate / MHZ) * od * n / (parent_rate / MHZ);  in ingenic_pll_calc()
152 	return div_u64((u64)parent_rate * m, n * od);  in ingenic_pll_calc()
171 		     unsigned long parent_rate)  in ingenic_pll_set_rate()  argument
186 	rate = ingenic_pll_calc(clk_info, req_rate, parent_rate,  in ingenic_pll_set_rate()
313 ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)  in ingenic_clk_recalc_rate()  argument
318 	unsigned long rate = parent_rate;  in ingenic_clk_recalc_rate()
337 		     unsigned long parent_rate, unsigned long req_rate)  in ingenic_clk_calc_div()  argument
342 	div = DIV_ROUND_UP(parent_rate, req_rate);  in ingenic_clk_calc_div()
353 		       unsigned long *parent_rate)  in ingenic_clk_round_rate()  argument
358 	long rate = *parent_rate;  in ingenic_clk_round_rate()
363 		rate /= ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);  in ingenic_clk_round_rate()
372 		     unsigned long parent_rate)  in ingenic_clk_set_rate()  argument
386 		div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);  in ingenic_clk_set_rate()
387 		rate = parent_rate / div;  in ingenic_clk_set_rate()