319 	u32 div_reg, div;  in ingenic_clk_recalc_rate()  local
324 		div_reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_recalc_rate()
325 		div = (div_reg >> clk_info->div.shift) &  in ingenic_clk_recalc_rate()
326 		      GENMASK(clk_info->div.bits - 1, 0);  in ingenic_clk_recalc_rate()
327 		div += 1;  in ingenic_clk_recalc_rate()
329 		rate /= div;  in ingenic_clk_recalc_rate()
339 	unsigned div;  in ingenic_clk_calc_div()  local
342 	div = DIV_ROUND_UP(parent_rate, req_rate);  in ingenic_clk_calc_div()
345 	div = min_t(unsigned, div, 1 << clk_info->div.bits);  in ingenic_clk_calc_div()
346 	div = max_t(unsigned, div, 1);  in ingenic_clk_calc_div()
348 	return div;  in ingenic_clk_calc_div()
365 		rate /= clk_info->fixdiv.div;  in ingenic_clk_round_rate()
379 	unsigned div, i;  in ingenic_clk_set_rate()  local
386 		div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);  in ingenic_clk_set_rate()
387 		rate = parent_rate / div;  in ingenic_clk_set_rate()
393 		reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
396 		mask = GENMASK(clk_info->div.bits - 1, 0);  in ingenic_clk_set_rate()
397 		reg &= ~(mask << clk_info->div.shift);  in ingenic_clk_set_rate()
398 		reg |= (div - 1) << clk_info->div.shift;  in ingenic_clk_set_rate()
401 		if (clk_info->div.stop_bit != -1)  in ingenic_clk_set_rate()
402 			reg &= ~BIT(clk_info->div.stop_bit);  in ingenic_clk_set_rate()
405 		if (clk_info->div.ce_bit != -1)  in ingenic_clk_set_rate()
406 			reg |= BIT(clk_info->div.ce_bit);  in ingenic_clk_set_rate()
409 		writel(reg, cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
412 		if (clk_info->div.busy_bit != -1) {  in ingenic_clk_set_rate()
414 				reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
415 				if (!(reg & BIT(clk_info->div.busy_bit)))  in ingenic_clk_set_rate()