334 	void __iomem *pll_base;  in mx50_clocks_init()  local
337 	pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);  in mx50_clocks_init()
338 	WARN_ON(!pll_base);  in mx50_clocks_init()
339 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx50_clocks_init()
341 	pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);  in mx50_clocks_init()
342 	WARN_ON(!pll_base);  in mx50_clocks_init()
343 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx50_clocks_init()
345 	pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);  in mx50_clocks_init()
346 	WARN_ON(!pll_base);  in mx50_clocks_init()
347 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx50_clocks_init()
396 	void __iomem *pll_base;  in mx51_clocks_init()  local
399 	pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);  in mx51_clocks_init()
400 	WARN_ON(!pll_base);  in mx51_clocks_init()
401 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx51_clocks_init()
403 	pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);  in mx51_clocks_init()
404 	WARN_ON(!pll_base);  in mx51_clocks_init()
405 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx51_clocks_init()
407 	pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);  in mx51_clocks_init()
408 	WARN_ON(!pll_base);  in mx51_clocks_init()
409 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx51_clocks_init()
485 	void __iomem *pll_base;  in mx53_clocks_init()  local
488 	pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);  in mx53_clocks_init()
489 	WARN_ON(!pll_base);  in mx53_clocks_init()
490 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx53_clocks_init()
492 	pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);  in mx53_clocks_init()
493 	WARN_ON(!pll_base);  in mx53_clocks_init()
494 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx53_clocks_init()
496 	pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);  in mx53_clocks_init()
497 	WARN_ON(!pll_base);  in mx53_clocks_init()
498 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx53_clocks_init()
500 	pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);  in mx53_clocks_init()
501 	WARN_ON(!pll_base);  in mx53_clocks_init()
502 	clk[IMX5_CLK_PLL4_SW]		= imx_clk_pllv2("pll4_sw", "osc", pll_base);  in mx53_clocks_init()