Lines Matching refs:clk_prepare_enable
313 clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); in mx5_clocks_common_init()
314 clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ in mx5_clocks_common_init()
315 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); in mx5_clocks_common_init()
316 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ in mx5_clocks_common_init()
317 clk_prepare_enable(clk[IMX5_CLK_SPBA]); in mx5_clocks_common_init()
318 clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ in mx5_clocks_common_init()
319 clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ in mx5_clocks_common_init()
320 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); in mx5_clocks_common_init()
321 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); in mx5_clocks_common_init()
322 clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); in mx5_clocks_common_init()
323 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); in mx5_clocks_common_init()
324 clk_prepare_enable(clk[IMX5_CLK_TMAX1]); in mx5_clocks_common_init()
325 clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ in mx5_clocks_common_init()
326 clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ in mx5_clocks_common_init()
384 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); in mx50_clocks_init()
461 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); in mx51_clocks_init()
579 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); in mx53_clocks_init()