Lines Matching refs:clk_register_clkdev

86 	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");  in mx1_clocks_init()
87 	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");  in mx1_clocks_init()
88 	clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");  in mx1_clocks_init()
89 	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");  in mx1_clocks_init()
90 	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");  in mx1_clocks_init()
91 	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");  in mx1_clocks_init()
92 	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");  in mx1_clocks_init()
93 	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");  in mx1_clocks_init()
94 	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");  in mx1_clocks_init()
95 	clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");  in mx1_clocks_init()
96 	clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");  in mx1_clocks_init()
97 	clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");  in mx1_clocks_init()
98 	clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");  in mx1_clocks_init()
99 	clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");  in mx1_clocks_init()
100 	clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");  in mx1_clocks_init()
101 	clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");  in mx1_clocks_init()
102 	clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");  in mx1_clocks_init()
103 	clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");  in mx1_clocks_init()