Lines Matching refs:parent_rate
83 unsigned long parent_rate) in xgene_clk_pll_recalc_rate() argument
101 fvco = parent_rate * (N_DIV_RD(pll) + 4); in xgene_clk_pll_recalc_rate()
111 fref = parent_rate / nref; in xgene_clk_pll_recalc_rate()
115 fvco / nout, parent_rate); in xgene_clk_pll_recalc_rate()
308 unsigned long parent_rate) in xgene_clk_recalc_rate() argument
321 parent_rate / data, parent_rate); in xgene_clk_recalc_rate()
323 return parent_rate / data; in xgene_clk_recalc_rate()
326 clk_hw_get_name(hw), parent_rate, parent_rate); in xgene_clk_recalc_rate()
327 return parent_rate; in xgene_clk_recalc_rate()
332 unsigned long parent_rate) in xgene_clk_set_rate() argument
345 if (rate > parent_rate) in xgene_clk_set_rate()
346 rate = parent_rate; in xgene_clk_set_rate()
347 divider_save = divider = parent_rate / rate; /* Rounded down */ in xgene_clk_set_rate()
359 parent_rate / divider_save); in xgene_clk_set_rate()
367 return parent_rate / divider_save; in xgene_clk_set_rate()
374 unsigned long parent_rate = *prate; in xgene_clk_round_rate() local
379 if (rate > parent_rate) in xgene_clk_round_rate()
380 rate = parent_rate; in xgene_clk_round_rate()
381 divider = parent_rate / rate; /* Rounded down */ in xgene_clk_round_rate()
386 return parent_rate / divider; in xgene_clk_round_rate()