163 static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)  in xgene_pllclk_init()  argument
165         const char *clk_name = np->full_name;  in xgene_pllclk_init()
169         reg = of_iomap(np, 0);  in xgene_pllclk_init()
171                 pr_err("Unable to map CSR register for %s\n", np->full_name);  in xgene_pllclk_init()
174         of_property_read_string(np, "clock-output-names", &clk_name);  in xgene_pllclk_init()
176                         clk_name, of_clk_get_parent_name(np, 0),  in xgene_pllclk_init()
179                 of_clk_add_provider(np, of_clk_src_simple_get, clk);  in xgene_pllclk_init()
185 static void xgene_socpllclk_init(struct device_node *np)  in xgene_socpllclk_init()  argument
187 	xgene_pllclk_init(np, PLL_TYPE_SOC);  in xgene_socpllclk_init()
190 static void xgene_pcppllclk_init(struct device_node *np)  in xgene_pcppllclk_init()  argument
192 	xgene_pllclk_init(np, PLL_TYPE_PCP);  in xgene_pcppllclk_init()
441 static void __init xgene_devclk_init(struct device_node *np)  in xgene_devclk_init()  argument
443 	const char *clk_name = np->full_name;  in xgene_devclk_init()
451         if (!of_device_is_available(np))  in xgene_devclk_init()
459 		rc = of_address_to_resource(np, i, &res);  in xgene_devclk_init()
463 					np->full_name);  in xgene_devclk_init()
468 		map_res = of_iomap(np, i);  in xgene_devclk_init()
471 				i, np->full_name);  in xgene_devclk_init()
479 	if (of_property_read_u32(np, "csr-offset", &parameters.reg_csr_offset))  in xgene_devclk_init()
481 	if (of_property_read_u32(np, "csr-mask", &parameters.reg_csr_mask))  in xgene_devclk_init()
483 	if (of_property_read_u32(np, "enable-offset",  in xgene_devclk_init()
486 	if (of_property_read_u32(np, "enable-mask", &parameters.reg_clk_mask))  in xgene_devclk_init()
488 	if (of_property_read_u32(np, "divider-offset",  in xgene_devclk_init()
491 	if (of_property_read_u32(np, "divider-width",  in xgene_devclk_init()
494 	if (of_property_read_u32(np, "divider-shift",  in xgene_devclk_init()
497 	of_property_read_string(np, "clock-output-names", &clk_name);  in xgene_devclk_init()
500 		of_clk_get_parent_name(np, 0), &parameters, &clk_lock);  in xgene_devclk_init()
504 	rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);  in xgene_devclk_init()
507 			np->full_name);  in xgene_devclk_init()