Lines Matching refs:divider_reg
202 void __iomem *divider_reg; /* CSR for divider */ member
313 if (pclk->param.divider_reg) { in xgene_clk_recalc_rate()
314 data = xgene_clk_read(pclk->param.divider_reg + in xgene_clk_recalc_rate()
343 if (pclk->param.divider_reg) { in xgene_clk_set_rate()
352 data = xgene_clk_read(pclk->param.divider_reg + in xgene_clk_set_rate()
356 xgene_clk_write(data, pclk->param.divider_reg + in xgene_clk_set_rate()
377 if (pclk->param.divider_reg) { in xgene_clk_round_rate()
456 parameters.divider_reg = NULL; in xgene_devclk_init()
475 parameters.divider_reg = map_res; in xgene_devclk_init()
514 if (parameters.divider_reg) in xgene_devclk_init()
515 iounmap(parameters.divider_reg); in xgene_devclk_init()