144 	u32 divisor;  in vt8500_dclk_round_rate()  local
149 	divisor = *prate / rate;  in vt8500_dclk_round_rate()
152 	if (rate * divisor < *prate)  in vt8500_dclk_round_rate()
153 		divisor++;  in vt8500_dclk_round_rate()
159 	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {  in vt8500_dclk_round_rate()
160 		divisor = 64 * ((divisor / 64) + 1);  in vt8500_dclk_round_rate()
163 	return *prate / divisor;  in vt8500_dclk_round_rate()
170 	u32 divisor;  in vt8500_dclk_set_rate()  local
176 	divisor =  parent_rate / rate;  in vt8500_dclk_set_rate()
178 	if (divisor == cdev->div_mask + 1)  in vt8500_dclk_set_rate()
179 		divisor = 0;  in vt8500_dclk_set_rate()
182 	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {  in vt8500_dclk_set_rate()
187 		divisor = 0x20 + (divisor / 64);  in vt8500_dclk_set_rate()
190 	if (divisor > cdev->div_mask) {  in vt8500_dclk_set_rate()
198 	writel(divisor, cdev->div_reg);  in vt8500_dclk_set_rate()