86 	struct clk_device *cdev = to_clk_device(hw);  in vt8500_dclk_enable()  local
90 	spin_lock_irqsave(cdev->lock, flags);  in vt8500_dclk_enable()
92 	en_val = readl(cdev->en_reg);  in vt8500_dclk_enable()
93 	en_val |= BIT(cdev->en_bit);  in vt8500_dclk_enable()
94 	writel(en_val, cdev->en_reg);  in vt8500_dclk_enable()
96 	spin_unlock_irqrestore(cdev->lock, flags);  in vt8500_dclk_enable()
102 	struct clk_device *cdev = to_clk_device(hw);  in vt8500_dclk_disable()  local
106 	spin_lock_irqsave(cdev->lock, flags);  in vt8500_dclk_disable()
108 	en_val = readl(cdev->en_reg);  in vt8500_dclk_disable()
109 	en_val &= ~BIT(cdev->en_bit);  in vt8500_dclk_disable()
110 	writel(en_val, cdev->en_reg);  in vt8500_dclk_disable()
112 	spin_unlock_irqrestore(cdev->lock, flags);  in vt8500_dclk_disable()
117 	struct clk_device *cdev = to_clk_device(hw);  in vt8500_dclk_is_enabled()  local
118 	u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));  in vt8500_dclk_is_enabled()
126 	struct clk_device *cdev = to_clk_device(hw);  in vt8500_dclk_recalc_rate()  local
127 	u32 div = readl(cdev->div_reg) & cdev->div_mask;  in vt8500_dclk_recalc_rate()
130 	if ((cdev->div_mask == 0x3F) && (div & BIT(5)))  in vt8500_dclk_recalc_rate()
135 		div = (cdev->div_mask + 1);  in vt8500_dclk_recalc_rate()
143 	struct clk_device *cdev = to_clk_device(hw);  in vt8500_dclk_round_rate()  local
159 	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {  in vt8500_dclk_round_rate()
169 	struct clk_device *cdev = to_clk_device(hw);  in vt8500_dclk_set_rate()  local
178 	if (divisor == cdev->div_mask + 1)  in vt8500_dclk_set_rate()
182 	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {  in vt8500_dclk_set_rate()
190 	if (divisor > cdev->div_mask) {  in vt8500_dclk_set_rate()
195 	spin_lock_irqsave(cdev->lock, flags);  in vt8500_dclk_set_rate()
198 	writel(divisor, cdev->div_reg);  in vt8500_dclk_set_rate()
201 	spin_unlock_irqrestore(cdev->lock, flags);  in vt8500_dclk_set_rate()