Lines Matching refs:STM32F4_RCC_APB2ENR
33 #define STM32F4_RCC_APB2ENR 0x44 macro
103 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
104 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
105 { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
106 { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
107 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
108 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
109 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
110 { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
111 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
112 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
113 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
114 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
115 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
116 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
117 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
118 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
119 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
120 { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },