Lines Matching refs:STM32F4_RCC_AHB1ENR
29 #define STM32F4_RCC_AHB1ENR 0x30 macro
44 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
45 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
46 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
47 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
48 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
49 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
50 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
51 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
52 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
53 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
54 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
55 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
56 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
57 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
58 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
59 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
60 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
61 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
62 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
63 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
64 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
65 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
66 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
357 8 * (gd->offset - STM32F4_RCC_AHB1ENR) + gd->bit_idx; in stm32f4_rcc_init()