43 	struct clockgen_pll_div div[4];  member
52 	int div;	/* PLL_DIVn */  member
355 		cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;  in p2041_init_periph()
357 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p2041_init_periph()
367 		cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;  in p4080_init_periph()
369 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
372 		cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;  in p4080_init_periph()
374 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
380 	int div = PLL_DIV2;  in p5020_init_periph()  local
384 		div = PLL_DIV4;  in p5020_init_periph()
387 		cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;  in p5020_init_periph()
389 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5020_init_periph()
395 	int div = PLL_DIV2;  in p5040_init_periph()  local
399 		div = PLL_DIV4;  in p5040_init_periph()
402 		cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;  in p5040_init_periph()
404 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()
407 		cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;  in p5040_init_periph()
409 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()
419 	cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;  in t1040_init_periph()
688 	int pll, div;  in get_pll_div()  local
694 	div = hwc->info->clksel[idx].div;  in get_pll_div()
696 	return &cg->pll[pll].div[div];  in get_pll_div()
708 	const struct clockgen_pll_div *div;  in create_mux_common()  local
720 		div = get_pll_div(cg, hwc, i);  in create_mux_common()
721 		if (!div)  in create_mux_common()
724 		rate = clk_get_rate(div->clk);  in create_mux_common()
732 		parent_names[j] = div->name;  in create_mux_common()
760 	const struct clockgen_pll_div *div;  in create_one_cmux()  local
780 	div = get_pll_div(cg, hwc, clksel);  in create_one_cmux()
781 	if (!div) {  in create_one_cmux()
786 	pct80_rate = clk_get_rate(div->clk);  in create_one_cmux()
790 	plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);  in create_one_cmux()
993 	for (i = 0; i < ARRAY_SIZE(pll->div); i++) {  in create_one_pll()
996 		snprintf(pll->div[i].name, sizeof(pll->div[i].name),  in create_one_pll()
1000 				pll->div[i].name, "cg-sysclk", 0, mult, i + 1);  in create_one_pll()
1003 			       __func__, pll->div[i].name, PTR_ERR(clk));  in create_one_pll()
1007 		pll->div[i].clk = clk;  in create_one_pll()
1031 	BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);  in legacy_pll_init()
1041 		subclks[0] = pll->div[0].clk;  in legacy_pll_init()
1042 		subclks[1] = pll->div[1].clk;  in legacy_pll_init()
1043 		subclks[2] = pll->div[3].clk;  in legacy_pll_init()
1045 		subclks[0] = pll->div[0].clk;  in legacy_pll_init()
1046 		subclks[1] = pll->div[1].clk;  in legacy_pll_init()
1047 		subclks[2] = pll->div[2].clk;  in legacy_pll_init()
1048 		subclks[3] = pll->div[3].clk;  in legacy_pll_init()
1133 		if (idx >= ARRAY_SIZE(pll->div))  in clockgen_clk_get()
1135 		clk = pll->div[idx].clk;  in clockgen_clk_get()