827 					     unsigned long parent_rate,  in bcm2835_pll_choose_ndiv_and_fdiv()  argument
833 	do_div(div, parent_rate);  in bcm2835_pll_choose_ndiv_and_fdiv()
839 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,  in bcm2835_pll_rate_from_divisors()  argument
847 	rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);  in bcm2835_pll_rate_from_divisors()
853 				   unsigned long *parent_rate)  in bcm2835_pll_round_rate()  argument
857 	bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);  in bcm2835_pll_round_rate()
859 	return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);  in bcm2835_pll_round_rate()
863 					  unsigned long parent_rate)  in bcm2835_pll_get_rate()  argument
872 	if (parent_rate == 0)  in bcm2835_pll_get_rate()
884 	return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);  in bcm2835_pll_get_rate()
951 				unsigned long rate, unsigned long parent_rate)  in bcm2835_pll_set_rate()  argument
975 	bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);  in bcm2835_pll_set_rate()
1055 					   unsigned long *parent_rate)  in bcm2835_pll_divider_round_rate()  argument
1057 	return clk_divider_ops.round_rate(hw, rate, parent_rate);  in bcm2835_pll_divider_round_rate()
1061 						  unsigned long parent_rate)  in bcm2835_pll_divider_get_rate()  argument
1072 	return parent_rate / div;  in bcm2835_pll_divider_get_rate()
1109 					unsigned long parent_rate)  in bcm2835_pll_divider_set_rate()  argument
1116 	div = DIV_ROUND_UP_ULL(parent_rate, rate);  in bcm2835_pll_divider_set_rate()
1167 				    unsigned long parent_rate)  in bcm2835_clock_choose_div()  argument
1172 	u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;  in bcm2835_clock_choose_div()
1194 					    unsigned long parent_rate,  in bcm2835_clock_rate_from_divisor()  argument
1210 	temp = (u64)parent_rate << data->frac_bits;  in bcm2835_clock_rate_from_divisor()
1219 				     unsigned long *parent_rate)  in bcm2835_clock_round_rate()  argument
1222 	u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate);  in bcm2835_clock_round_rate()
1224 	return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div);  in bcm2835_clock_round_rate()
1228 					    unsigned long parent_rate)  in bcm2835_clock_get_rate()  argument
1235 	return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);  in bcm2835_clock_get_rate()
1286 				  unsigned long rate, unsigned long parent_rate)  in bcm2835_clock_set_rate()  argument
1291 	u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);  in bcm2835_clock_set_rate()