830 	u64 div;  in bcm2835_pll_choose_ndiv_and_fdiv()  local
832 	div = (u64)rate << A2W_PLL_FRAC_BITS;  in bcm2835_pll_choose_ndiv_and_fdiv()
833 	do_div(div, parent_rate);  in bcm2835_pll_choose_ndiv_and_fdiv()
835 	*ndiv = div >> A2W_PLL_FRAC_BITS;  in bcm2835_pll_choose_ndiv_and_fdiv()
836 	*fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);  in bcm2835_pll_choose_ndiv_and_fdiv()
1033 	struct clk_divider div;  member
1041 	return container_of(hw, struct bcm2835_pll_divider, div.hw);  in bcm2835_pll_divider_from_hw()
1066 	u32 div = cprman_read(cprman, data->a2w_reg);  in bcm2835_pll_divider_get_rate()  local
1068 	div &= (1 << A2W_PLL_DIV_BITS) - 1;  in bcm2835_pll_divider_get_rate()
1069 	if (div == 0)  in bcm2835_pll_divider_get_rate()
1070 		div = 256;  in bcm2835_pll_divider_get_rate()
1072 	return parent_rate / div;  in bcm2835_pll_divider_get_rate()
1114 	u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;  in bcm2835_pll_divider_set_rate()  local
1116 	div = DIV_ROUND_UP_ULL(parent_rate, rate);  in bcm2835_pll_divider_set_rate()
1118 	div = min(div, max_div);  in bcm2835_pll_divider_set_rate()
1119 	if (div == max_div)  in bcm2835_pll_divider_set_rate()
1120 		div = 0;  in bcm2835_pll_divider_set_rate()
1122 	cprman_write(cprman, data->a2w_reg, div);  in bcm2835_pll_divider_set_rate()
1173 	u32 div;  in bcm2835_clock_choose_div()  local
1176 	div = temp;  in bcm2835_clock_choose_div()
1180 		div += unused_frac_mask >> 1;  in bcm2835_clock_choose_div()
1181 		div &= ~unused_frac_mask;  in bcm2835_clock_choose_div()
1185 	div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);  in bcm2835_clock_choose_div()
1187 	div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,  in bcm2835_clock_choose_div()
1190 	return div;  in bcm2835_clock_choose_div()
1195 					    u32 div)  in bcm2835_clock_rate_from_divisor()  argument
1204 	div >>= CM_DIV_FRAC_BITS - data->frac_bits;  in bcm2835_clock_rate_from_divisor()
1205 	div &= (1 << (data->int_bits + data->frac_bits)) - 1;  in bcm2835_clock_rate_from_divisor()
1207 	if (div == 0)  in bcm2835_clock_rate_from_divisor()
1212 	do_div(temp, div);  in bcm2835_clock_rate_from_divisor()
1222 	u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate);  in bcm2835_clock_round_rate()  local
1224 	return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div);  in bcm2835_clock_round_rate()
1233 	u32 div = cprman_read(cprman, data->div_reg);  in bcm2835_clock_get_rate()  local
1235 	return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);  in bcm2835_clock_get_rate()
1291 	u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);  in bcm2835_clock_set_rate()  local
1293 	cprman_write(cprman, data->div_reg, div);  in bcm2835_clock_set_rate()
1379 	divider->div.reg = cprman->regs + data->a2w_reg;  in bcm2835_register_pll_divider()
1380 	divider->div.shift = A2W_PLL_DIV_SHIFT;  in bcm2835_register_pll_divider()
1381 	divider->div.width = A2W_PLL_DIV_BITS;  in bcm2835_register_pll_divider()
1382 	divider->div.flags = 0;  in bcm2835_register_pll_divider()
1383 	divider->div.lock = &cprman->regs_lock;  in bcm2835_register_pll_divider()
1384 	divider->div.hw.init = &init;  in bcm2835_register_pll_divider()
1385 	divider->div.table = NULL;  in bcm2835_register_pll_divider()
1390 	clk = devm_clk_register(cprman->dev, &divider->div.hw);  in bcm2835_register_pll_divider()