Lines Matching refs:channel
134 struct xilly_channel *channel; in xillybus_isr() local
194 channel = ep->channels[msg_channel]; in xillybus_isr()
197 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
201 spin_lock(&channel->wr_spinlock); in xillybus_isr()
202 channel->wr_buffers[msg_bufno]->end_offset = in xillybus_isr()
204 channel->wr_fpga_buf_idx = msg_bufno; in xillybus_isr()
205 channel->wr_empty = 0; in xillybus_isr()
206 channel->wr_sleepy = 0; in xillybus_isr()
207 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
209 wake_up_interruptible(&channel->wr_wait); in xillybus_isr()
214 if (msg_bufno >= channel->num_rd_buffers) { in xillybus_isr()
219 spin_lock(&channel->rd_spinlock); in xillybus_isr()
220 channel->rd_fpga_buf_idx = msg_bufno; in xillybus_isr()
221 channel->rd_full = 0; in xillybus_isr()
222 spin_unlock(&channel->rd_spinlock); in xillybus_isr()
224 wake_up_interruptible(&channel->rd_wait); in xillybus_isr()
225 if (!channel->rd_synchronous) in xillybus_isr()
228 &channel->rd_workitem, in xillybus_isr()
241 channel = ep->channels[msg_channel]; in xillybus_isr()
243 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
247 spin_lock(&channel->wr_spinlock); in xillybus_isr()
248 if (msg_bufno == channel->wr_host_buf_idx) in xillybus_isr()
249 channel->wr_ready = 1; in xillybus_isr()
250 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
252 wake_up_interruptible(&channel->wr_ready_wait); in xillybus_isr()
267 channel = ep->channels[msg_channel]; in xillybus_isr()
268 spin_lock(&channel->wr_spinlock); in xillybus_isr()
269 channel->wr_eof = msg_bufno; in xillybus_isr()
270 channel->wr_sleepy = 0; in xillybus_isr()
272 channel->wr_hangup = channel->wr_empty && in xillybus_isr()
273 (channel->wr_host_buf_idx == msg_bufno); in xillybus_isr()
275 spin_unlock(&channel->wr_spinlock); in xillybus_isr()
277 wake_up_interruptible(&channel->wr_wait); in xillybus_isr()
411 struct xilly_channel *channel; in xilly_setupchannels() local
434 channel = devm_kcalloc(dev, ep->num_channels, in xilly_setupchannels()
436 if (!channel) in xilly_setupchannels()
450 channel->wr_buffers = NULL; in xilly_setupchannels()
451 channel->rd_buffers = NULL; in xilly_setupchannels()
452 channel->num_wr_buffers = 0; in xilly_setupchannels()
453 channel->num_rd_buffers = 0; in xilly_setupchannels()
454 channel->wr_fpga_buf_idx = -1; in xilly_setupchannels()
455 channel->wr_host_buf_idx = 0; in xilly_setupchannels()
456 channel->wr_host_buf_pos = 0; in xilly_setupchannels()
457 channel->wr_empty = 1; in xilly_setupchannels()
458 channel->wr_ready = 0; in xilly_setupchannels()
459 channel->wr_sleepy = 1; in xilly_setupchannels()
460 channel->rd_fpga_buf_idx = 0; in xilly_setupchannels()
461 channel->rd_host_buf_idx = 0; in xilly_setupchannels()
462 channel->rd_host_buf_pos = 0; in xilly_setupchannels()
463 channel->rd_full = 0; in xilly_setupchannels()
464 channel->wr_ref_count = 0; in xilly_setupchannels()
465 channel->rd_ref_count = 0; in xilly_setupchannels()
467 spin_lock_init(&channel->wr_spinlock); in xilly_setupchannels()
468 spin_lock_init(&channel->rd_spinlock); in xilly_setupchannels()
469 mutex_init(&channel->wr_mutex); in xilly_setupchannels()
470 mutex_init(&channel->rd_mutex); in xilly_setupchannels()
471 init_waitqueue_head(&channel->rd_wait); in xilly_setupchannels()
472 init_waitqueue_head(&channel->wr_wait); in xilly_setupchannels()
473 init_waitqueue_head(&channel->wr_ready_wait); in xilly_setupchannels()
475 INIT_DELAYED_WORK(&channel->rd_workitem, xillybus_autoflush); in xilly_setupchannels()
477 channel->endpoint = ep; in xilly_setupchannels()
478 channel->chan_num = i; in xilly_setupchannels()
480 channel->log2_element_size = 0; in xilly_setupchannels()
482 ep->channels[i] = channel++; in xilly_setupchannels()
506 channel = ep->channels[channelnum]; /* NULL for msg channel */ in xilly_setupchannels()
509 channel->log2_element_size = ((format > 2) ? in xilly_setupchannels()
512 bytebufsize = channel->rd_buf_size = bufsize * in xilly_setupchannels()
513 (1 << channel->log2_element_size); in xilly_setupchannels()
525 channel->num_rd_buffers = bufnum; in xilly_setupchannels()
526 channel->rd_allow_partial = allowpartial; in xilly_setupchannels()
527 channel->rd_synchronous = synchronous; in xilly_setupchannels()
528 channel->rd_exclusive_open = exclusive_open; in xilly_setupchannels()
529 channel->seekable = seekable; in xilly_setupchannels()
531 channel->rd_buffers = buffers; in xilly_setupchannels()
535 channel->num_wr_buffers = bufnum; in xilly_setupchannels()
537 channel->seekable = seekable; in xilly_setupchannels()
538 channel->wr_supports_nonempty = supports_nonempty; in xilly_setupchannels()
540 channel->wr_allow_partial = allowpartial; in xilly_setupchannels()
541 channel->wr_synchronous = synchronous; in xilly_setupchannels()
542 channel->wr_exclusive_open = exclusive_open; in xilly_setupchannels()
544 channel->wr_buffers = buffers; in xilly_setupchannels()
610 struct xilly_channel *channel; in xilly_obtain_idt() local
614 channel = endpoint->channels[1]; /* This should be generated ad-hoc */ in xilly_obtain_idt()
616 channel->wr_sleepy = 1; in xilly_obtain_idt()
622 t = wait_event_interruptible_timeout(channel->wr_wait, in xilly_obtain_idt()
623 (!channel->wr_sleepy), in xilly_obtain_idt()
636 channel->endpoint, in xilly_obtain_idt()
637 channel->wr_buffers[0]->dma_addr, in xilly_obtain_idt()
638 channel->wr_buf_size, in xilly_obtain_idt()
641 if (channel->wr_buffers[0]->end_offset != endpoint->idtlen) { in xilly_obtain_idt()
644 channel->wr_buffers[0]->end_offset, endpoint->idtlen); in xilly_obtain_idt()
648 if (crc32_le(~0, channel->wr_buffers[0]->addr, in xilly_obtain_idt()
654 version = channel->wr_buffers[0]->addr; in xilly_obtain_idt()
675 struct xilly_channel *channel = filp->private_data; in xillybus_read() local
683 if (channel->endpoint->fatal_error) in xillybus_read()
688 rc = mutex_lock_interruptible(&channel->wr_mutex); in xillybus_read()
695 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_read()
697 empty = channel->wr_empty; in xillybus_read()
698 ready = !empty || channel->wr_ready; in xillybus_read()
701 bufidx = channel->wr_host_buf_idx; in xillybus_read()
702 bufpos = channel->wr_host_buf_pos; in xillybus_read()
703 howmany = ((channel->wr_buffers[bufidx]->end_offset in xillybus_read()
704 + 1) << channel->log2_element_size) in xillybus_read()
712 channel->wr_host_buf_pos += howmany; in xillybus_read()
716 channel->wr_host_buf_pos = 0; in xillybus_read()
718 if (bufidx == channel->wr_fpga_buf_idx) { in xillybus_read()
719 channel->wr_empty = 1; in xillybus_read()
720 channel->wr_sleepy = 1; in xillybus_read()
721 channel->wr_ready = 0; in xillybus_read()
724 if (bufidx >= (channel->num_wr_buffers - 1)) in xillybus_read()
725 channel->wr_host_buf_idx = 0; in xillybus_read()
727 channel->wr_host_buf_idx++; in xillybus_read()
739 reached_eof = channel->wr_empty && in xillybus_read()
740 (channel->wr_host_buf_idx == channel->wr_eof); in xillybus_read()
741 channel->wr_hangup = reached_eof; in xillybus_read()
742 exhausted = channel->wr_empty; in xillybus_read()
743 waiting_bufidx = channel->wr_host_buf_idx; in xillybus_read()
745 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_read()
750 channel->endpoint->ephw->hw_sync_sgl_for_cpu( in xillybus_read()
751 channel->endpoint, in xillybus_read()
752 channel->wr_buffers[bufidx]->dma_addr, in xillybus_read()
753 channel->wr_buf_size, in xillybus_read()
758 channel->wr_buffers[bufidx]->addr in xillybus_read()
766 channel->endpoint->ephw->hw_sync_sgl_for_device( in xillybus_read()
767 channel->endpoint, in xillybus_read()
768 channel->wr_buffers[bufidx]->dma_addr, in xillybus_read()
769 channel->wr_buf_size, in xillybus_read()
780 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
782 channel->endpoint->registers + in xillybus_read()
787 mutex_unlock(&channel->wr_mutex); in xillybus_read()
801 (channel->wr_synchronous && channel->wr_allow_partial))) in xillybus_read()
831 channel->log2_element_size; in xillybus_read()
832 int buf_elements = channel->wr_buf_size >> in xillybus_read()
833 channel->log2_element_size; in xillybus_read()
840 if (channel->wr_synchronous) { in xillybus_read()
842 if (channel->wr_allow_partial && in xillybus_read()
847 if (!channel->wr_allow_partial && in xillybus_read()
849 (buf_elements * channel->num_wr_buffers))) in xillybus_read()
851 channel->num_wr_buffers - 1; in xillybus_read()
862 if (channel->wr_synchronous || in xillybus_read()
864 mutex_lock(&channel->endpoint->register_mutex); in xillybus_read()
867 channel->endpoint->registers + in xillybus_read()
870 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
873 channel->endpoint->registers + in xillybus_read()
876 mutex_unlock(&channel->endpoint-> in xillybus_read()
887 if (!channel->wr_allow_partial || in xillybus_read()
896 mutex_unlock(&channel->wr_mutex); in xillybus_read()
899 channel->wr_wait, in xillybus_read()
900 (!channel->wr_sleepy))) in xillybus_read()
904 &channel->wr_mutex)) in xillybus_read()
906 } while (channel->wr_sleepy); in xillybus_read()
911 if (channel->endpoint->fatal_error) in xillybus_read()
931 channel->wr_wait, in xillybus_read()
932 (!channel->wr_sleepy), in xillybus_read()
939 mutex_unlock(&channel->wr_mutex); in xillybus_read()
940 if (channel->endpoint->fatal_error) in xillybus_read()
959 iowrite32(1 | (channel->chan_num << 1) | in xillybus_read()
962 channel->endpoint->registers + in xillybus_read()
975 mutex_unlock(&channel->wr_mutex); in xillybus_read()
977 if (channel->endpoint->fatal_error) in xillybus_read()
993 static int xillybus_myflush(struct xilly_channel *channel, long timeout) in xillybus_myflush() argument
1004 if (channel->endpoint->fatal_error) in xillybus_myflush()
1006 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_myflush()
1016 if (!channel->rd_ref_count) in xillybus_myflush()
1019 bufidx = channel->rd_host_buf_idx; in xillybus_myflush()
1022 channel->num_rd_buffers - 1 : in xillybus_myflush()
1025 end_offset_plus1 = channel->rd_host_buf_pos >> in xillybus_myflush()
1026 channel->log2_element_size; in xillybus_myflush()
1028 new_rd_host_buf_pos = channel->rd_host_buf_pos - in xillybus_myflush()
1029 (end_offset_plus1 << channel->log2_element_size); in xillybus_myflush()
1033 unsigned char *tail = channel->rd_buffers[bufidx]->addr + in xillybus_myflush()
1034 (end_offset_plus1 << channel->log2_element_size); in xillybus_myflush()
1038 channel->rd_leftovers[i] = *tail++; in xillybus_myflush()
1040 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_myflush()
1045 (channel->rd_full || in xillybus_myflush()
1046 (bufidx_minus1 != channel->rd_fpga_buf_idx))) { in xillybus_myflush()
1047 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1057 channel->rd_leftovers[3] = (new_rd_host_buf_pos != 0); in xillybus_myflush()
1061 if (bufidx == channel->rd_fpga_buf_idx) in xillybus_myflush()
1062 channel->rd_full = 1; in xillybus_myflush()
1063 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1065 if (bufidx >= (channel->num_rd_buffers - 1)) in xillybus_myflush()
1066 channel->rd_host_buf_idx = 0; in xillybus_myflush()
1068 channel->rd_host_buf_idx++; in xillybus_myflush()
1070 channel->endpoint->ephw->hw_sync_sgl_for_device( in xillybus_myflush()
1071 channel->endpoint, in xillybus_myflush()
1072 channel->rd_buffers[bufidx]->dma_addr, in xillybus_myflush()
1073 channel->rd_buf_size, in xillybus_myflush()
1076 mutex_lock(&channel->endpoint->register_mutex); in xillybus_myflush()
1079 channel->endpoint->registers + fpga_buf_offset_reg); in xillybus_myflush()
1081 iowrite32((channel->chan_num << 1) | /* Channel ID */ in xillybus_myflush()
1084 channel->endpoint->registers + fpga_buf_ctrl_reg); in xillybus_myflush()
1086 mutex_unlock(&channel->endpoint->register_mutex); in xillybus_myflush()
1088 bufidx = channel->num_rd_buffers - 1; in xillybus_myflush()
1093 channel->rd_host_buf_pos = new_rd_host_buf_pos; in xillybus_myflush()
1107 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_myflush()
1109 if (bufidx != channel->rd_fpga_buf_idx) in xillybus_myflush()
1110 channel->rd_full = 1; /* in xillybus_myflush()
1115 empty = !channel->rd_full; in xillybus_myflush()
1117 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_myflush()
1128 wait_event_interruptible(channel->rd_wait, in xillybus_myflush()
1129 (!channel->rd_full)); in xillybus_myflush()
1132 channel->rd_wait, in xillybus_myflush()
1133 (!channel->rd_full), in xillybus_myflush()
1135 dev_warn(channel->endpoint->dev, in xillybus_myflush()
1142 if (channel->rd_full) { in xillybus_myflush()
1149 mutex_unlock(&channel->rd_mutex); in xillybus_myflush()
1151 if (channel->endpoint->fatal_error) in xillybus_myflush()
1169 struct xilly_channel *channel = container_of( in xillybus_autoflush() local
1173 rc = xillybus_myflush(channel, -1); in xillybus_autoflush()
1175 dev_warn(channel->endpoint->dev, in xillybus_autoflush()
1178 dev_err(channel->endpoint->dev, in xillybus_autoflush()
1188 struct xilly_channel *channel = filp->private_data; in xillybus_write() local
1196 if (channel->endpoint->fatal_error) in xillybus_write()
1199 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_write()
1206 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_write()
1208 full = channel->rd_full; in xillybus_write()
1211 bufidx = channel->rd_host_buf_idx; in xillybus_write()
1212 bufpos = channel->rd_host_buf_pos; in xillybus_write()
1213 howmany = channel->rd_buf_size - bufpos; in xillybus_write()
1223 ((bufpos >> channel->log2_element_size) == 0))) { in xillybus_write()
1227 channel->rd_host_buf_pos += howmany; in xillybus_write()
1233 channel->rd_buf_size >> in xillybus_write()
1234 channel->log2_element_size; in xillybus_write()
1235 channel->rd_host_buf_pos = 0; in xillybus_write()
1243 channel->log2_element_size; in xillybus_write()
1245 channel->rd_host_buf_pos -= in xillybus_write()
1247 channel->log2_element_size; in xillybus_write()
1249 tail = channel-> in xillybus_write()
1252 channel->log2_element_size); in xillybus_write()
1255 i < channel->rd_host_buf_pos; in xillybus_write()
1257 channel->rd_leftovers[i] = in xillybus_write()
1261 if (bufidx == channel->rd_fpga_buf_idx) in xillybus_write()
1262 channel->rd_full = 1; in xillybus_write()
1264 if (bufidx >= (channel->num_rd_buffers - 1)) in xillybus_write()
1265 channel->rd_host_buf_idx = 0; in xillybus_write()
1267 channel->rd_host_buf_idx++; in xillybus_write()
1279 exhausted = channel->rd_full; in xillybus_write()
1281 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_write()
1285 channel->rd_buffers[bufidx]->addr; in xillybus_write()
1289 (channel->rd_leftovers[3] != 0)) { in xillybus_write()
1290 channel->endpoint->ephw->hw_sync_sgl_for_cpu( in xillybus_write()
1291 channel->endpoint, in xillybus_write()
1292 channel->rd_buffers[bufidx]->dma_addr, in xillybus_write()
1293 channel->rd_buf_size, in xillybus_write()
1298 *head++ = channel->rd_leftovers[i]; in xillybus_write()
1300 channel->rd_leftovers[3] = 0; /* Clear flag */ in xillybus_write()
1304 channel->rd_buffers[bufidx]->addr + bufpos, in xillybus_write()
1312 channel->endpoint->ephw->hw_sync_sgl_for_device( in xillybus_write()
1313 channel->endpoint, in xillybus_write()
1314 channel->rd_buffers[bufidx]->dma_addr, in xillybus_write()
1315 channel->rd_buf_size, in xillybus_write()
1318 mutex_lock(&channel->endpoint->register_mutex); in xillybus_write()
1321 channel->endpoint->registers + in xillybus_write()
1324 iowrite32((channel->chan_num << 1) | in xillybus_write()
1327 channel->endpoint->registers + in xillybus_write()
1330 mutex_unlock(&channel->endpoint-> in xillybus_write()
1333 channel->rd_leftovers[3] = in xillybus_write()
1334 (channel->rd_host_buf_pos != 0); in xillybus_write()
1338 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1340 if (channel->endpoint->fatal_error) in xillybus_write()
1343 if (!channel->rd_synchronous) in xillybus_write()
1346 &channel->rd_workitem, in xillybus_write()
1359 if ((bytes_done > 0) && channel->rd_allow_partial) in xillybus_write()
1373 if (wait_event_interruptible(channel->rd_wait, in xillybus_write()
1374 (!channel->rd_full))) { in xillybus_write()
1375 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1377 if (channel->endpoint->fatal_error) in xillybus_write()
1386 mutex_unlock(&channel->rd_mutex); in xillybus_write()
1388 if (!channel->rd_synchronous) in xillybus_write()
1390 &channel->rd_workitem, in xillybus_write()
1393 if (channel->endpoint->fatal_error) in xillybus_write()
1399 if ((channel->rd_synchronous) && (bytes_done > 0)) { in xillybus_write()
1416 struct xilly_channel *channel; in xillybus_open() local
1440 channel = endpoint->channels[1 + minor - endpoint->lowest_minor]; in xillybus_open()
1441 filp->private_data = channel; in xillybus_open()
1449 if ((filp->f_mode & FMODE_READ) && (!channel->num_wr_buffers)) in xillybus_open()
1452 if ((filp->f_mode & FMODE_WRITE) && (!channel->num_rd_buffers)) in xillybus_open()
1456 (channel->wr_synchronous || !channel->wr_allow_partial || in xillybus_open()
1457 !channel->wr_supports_nonempty)) { in xillybus_open()
1464 (channel->rd_synchronous || !channel->rd_allow_partial)) { in xillybus_open()
1478 rc = mutex_lock_interruptible(&channel->wr_mutex); in xillybus_open()
1484 rc = mutex_lock_interruptible(&channel->rd_mutex); in xillybus_open()
1490 (channel->wr_ref_count != 0) && in xillybus_open()
1491 (channel->wr_exclusive_open)) { in xillybus_open()
1497 (channel->rd_ref_count != 0) && in xillybus_open()
1498 (channel->rd_exclusive_open)) { in xillybus_open()
1504 if (channel->wr_ref_count == 0) { /* First open of file */ in xillybus_open()
1506 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_open()
1507 channel->wr_host_buf_idx = 0; in xillybus_open()
1508 channel->wr_host_buf_pos = 0; in xillybus_open()
1509 channel->wr_fpga_buf_idx = -1; in xillybus_open()
1510 channel->wr_empty = 1; in xillybus_open()
1511 channel->wr_ready = 0; in xillybus_open()
1512 channel->wr_sleepy = 1; in xillybus_open()
1513 channel->wr_eof = -1; in xillybus_open()
1514 channel->wr_hangup = 0; in xillybus_open()
1516 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_open()
1518 iowrite32(1 | (channel->chan_num << 1) | in xillybus_open()
1520 ((channel->wr_synchronous & 1) << 23), in xillybus_open()
1521 channel->endpoint->registers + in xillybus_open()
1525 channel->wr_ref_count++; in xillybus_open()
1529 if (channel->rd_ref_count == 0) { /* First open of file */ in xillybus_open()
1531 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_open()
1532 channel->rd_host_buf_idx = 0; in xillybus_open()
1533 channel->rd_host_buf_pos = 0; in xillybus_open()
1534 channel->rd_leftovers[3] = 0; /* No leftovers. */ in xillybus_open()
1535 channel->rd_fpga_buf_idx = channel->num_rd_buffers - 1; in xillybus_open()
1536 channel->rd_full = 0; in xillybus_open()
1538 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_open()
1540 iowrite32((channel->chan_num << 1) | in xillybus_open()
1542 channel->endpoint->registers + in xillybus_open()
1546 channel->rd_ref_count++; in xillybus_open()
1551 mutex_unlock(&channel->rd_mutex); in xillybus_open()
1554 mutex_unlock(&channel->wr_mutex); in xillybus_open()
1556 if (!rc && (!channel->seekable)) in xillybus_open()
1565 struct xilly_channel *channel = filp->private_data; in xillybus_release() local
1570 if (channel->endpoint->fatal_error) in xillybus_release()
1574 mutex_lock(&channel->rd_mutex); in xillybus_release()
1576 channel->rd_ref_count--; in xillybus_release()
1578 if (channel->rd_ref_count == 0) { in xillybus_release()
1584 iowrite32((channel->chan_num << 1) | /* Channel ID */ in xillybus_release()
1586 channel->endpoint->registers + in xillybus_release()
1589 mutex_unlock(&channel->rd_mutex); in xillybus_release()
1593 mutex_lock(&channel->wr_mutex); in xillybus_release()
1595 channel->wr_ref_count--; in xillybus_release()
1597 if (channel->wr_ref_count == 0) { in xillybus_release()
1598 iowrite32(1 | (channel->chan_num << 1) | in xillybus_release()
1600 channel->endpoint->registers + in xillybus_release()
1614 spin_lock_irqsave(&channel->wr_spinlock, in xillybus_release()
1616 buf_idx = channel->wr_fpga_buf_idx; in xillybus_release()
1617 eof = channel->wr_eof; in xillybus_release()
1618 channel->wr_sleepy = 1; in xillybus_release()
1619 spin_unlock_irqrestore(&channel->wr_spinlock, in xillybus_release()
1629 if (buf_idx == channel->num_wr_buffers) in xillybus_release()
1644 channel->wr_wait, in xillybus_release()
1645 (!channel->wr_sleepy))) in xillybus_release()
1648 if (channel->wr_sleepy) { in xillybus_release()
1649 mutex_unlock(&channel->wr_mutex); in xillybus_release()
1650 dev_warn(channel->endpoint->dev, in xillybus_release()
1657 mutex_unlock(&channel->wr_mutex); in xillybus_release()
1665 struct xilly_channel *channel = filp->private_data; in xillybus_llseek() local
1676 if (channel->endpoint->fatal_error) in xillybus_llseek()
1679 mutex_lock(&channel->wr_mutex); in xillybus_llseek()
1680 mutex_lock(&channel->rd_mutex); in xillybus_llseek()
1698 if (pos & ((1 << channel->log2_element_size) - 1)) { in xillybus_llseek()
1703 mutex_lock(&channel->endpoint->register_mutex); in xillybus_llseek()
1705 iowrite32(pos >> channel->log2_element_size, in xillybus_llseek()
1706 channel->endpoint->registers + fpga_buf_offset_reg); in xillybus_llseek()
1708 iowrite32((channel->chan_num << 1) | in xillybus_llseek()
1710 channel->endpoint->registers + fpga_buf_ctrl_reg); in xillybus_llseek()
1712 mutex_unlock(&channel->endpoint->register_mutex); in xillybus_llseek()
1715 mutex_unlock(&channel->rd_mutex); in xillybus_llseek()
1716 mutex_unlock(&channel->wr_mutex); in xillybus_llseek()
1732 channel->rd_leftovers[3] = 0; in xillybus_llseek()
1739 struct xilly_channel *channel = filp->private_data; in xillybus_poll() local
1743 poll_wait(filp, &channel->endpoint->ep_wait, wait); in xillybus_poll()
1753 if (!channel->wr_synchronous && channel->wr_supports_nonempty) { in xillybus_poll()
1754 poll_wait(filp, &channel->wr_wait, wait); in xillybus_poll()
1755 poll_wait(filp, &channel->wr_ready_wait, wait); in xillybus_poll()
1757 spin_lock_irqsave(&channel->wr_spinlock, flags); in xillybus_poll()
1758 if (!channel->wr_empty || channel->wr_ready) in xillybus_poll()
1761 if (channel->wr_hangup) in xillybus_poll()
1768 spin_unlock_irqrestore(&channel->wr_spinlock, flags); in xillybus_poll()
1777 if (channel->rd_allow_partial) { in xillybus_poll()
1778 poll_wait(filp, &channel->rd_wait, wait); in xillybus_poll()
1780 spin_lock_irqsave(&channel->rd_spinlock, flags); in xillybus_poll()
1781 if (!channel->rd_full) in xillybus_poll()
1783 spin_unlock_irqrestore(&channel->rd_spinlock, flags); in xillybus_poll()
1786 if (channel->endpoint->fatal_error) in xillybus_poll()