Lines Matching defs:xilly_channel

46 struct xilly_channel {  struct
47 	struct xilly_endpoint *endpoint;
48 	int chan_num;
49 	int log2_element_size;
50 	int seekable;
52 	struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
53 	int num_wr_buffers;
54 	unsigned int wr_buf_size; /* In bytes */
55 	int wr_fpga_buf_idx;
56 	int wr_host_buf_idx;
57 	int wr_host_buf_pos;
58 	int wr_empty;
59 	int wr_ready; /* Significant only when wr_empty == 1 */
60 	int wr_sleepy;
61 	int wr_eof;
62 	int wr_hangup;
63 	spinlock_t wr_spinlock;
64 	struct mutex wr_mutex;
65 	wait_queue_head_t wr_wait;
66 	wait_queue_head_t wr_ready_wait;
67 	int wr_ref_count;
68 	int wr_synchronous;
69 	int wr_allow_partial;
70 	int wr_exclusive_open;
71 	int wr_supports_nonempty;
73 	struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
74 	int num_rd_buffers;
75 	unsigned int rd_buf_size; /* In bytes */
76 	int rd_fpga_buf_idx;
77 	int rd_host_buf_pos;
78 	int rd_host_buf_idx;
79 	int rd_full;
80 	spinlock_t rd_spinlock;
81 	struct mutex rd_mutex;
82 	wait_queue_head_t rd_wait;
83 	int rd_ref_count;
84 	int rd_allow_partial;
85 	int rd_synchronous;
86 	int rd_exclusive_open;
87 	struct delayed_work rd_workitem;
88 	unsigned char rd_leftovers[4];