322 #define read_reg(info, reg) inb((info)->io_base + (reg))  macro
329 		 (unsigned char) (read_reg(info, (reg)) | (mask)))
332 		 (unsigned char) (read_reg(info, (reg)) & ~(mask)))
690 	while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {  in wait_command_complete()
853 		fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);  in rx_ready_hdlc()
862 			data[0] = read_reg(info, CHA + RXFIFO);  in rx_ready_hdlc()
903 		fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);  in rx_ready_async()
908 		if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))  in rx_ready_async()
916 		data   = read_reg(info, CHA + RXFIFO);  in rx_ready_async()
917 		status = read_reg(info, CHA + RXFIFO);  in rx_ready_async()
1175 	while ((gis = read_reg(info, CHA + GIS))) {  in mgslpc_isr()
1236 			pis = read_reg(info, CHA + PIS);  in mgslpc_isr()
1881 	val = read_reg(info, PVR) & 0x0f;  in set_interface()
2923 		val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;  in mgslpc_set_rate()
3023 	val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0);  in loopback_enable()
3027 	val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5);  in loopback_enable()
3037 	val = read_reg(info, CHA + MODE) | BIT0;  in loopback_enable()
3601 	if (read_reg(info, CHB + VSTR) & BIT7)  in get_signals()
3603 	if (read_reg(info, CHB + STAR) & BIT1)  in get_signals()
3606 	status = read_reg(info, CHA + PVR);  in get_signals()
3620 	val = read_reg(info, CHA + MODE);  in set_signals()
3758 		if ((read_reg(info, XAD1) != patterns[i]) ||  in register_test()
3759 		    (read_reg(info, XAD2) != patterns[(i + 1) % count])) {  in register_test()