Lines Matching refs:src
63 #define MAJOR_HW_REV_RD(src) (((src) & 0x0f000000) >> 24) argument
64 #define MINOR_HW_REV_RD(src) (((src) & 0x00f00000) >> 20) argument
65 #define HW_PATCH_LEVEL_RD(src) (((src) & 0x000f0000) >> 16) argument
66 #define MAX_REFILL_CYCLES_SET(dst, src) \ argument
67 ((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000))
68 #define MIN_REFILL_CYCLES_SET(dst, src) \ argument
69 ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
70 #define ALARM_THRESHOLD_SET(dst, src) \ argument
71 ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
72 #define ENABLE_RNG_SET(dst, src) \ argument
73 ((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10)))
74 #define REGSPEC_TEST_MODE_SET(dst, src) \ argument
75 ((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8)))
76 #define MONOBIT_FAIL_MASK_SET(dst, src) \ argument
77 ((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7)))
78 #define POKER_FAIL_MASK_SET(dst, src) \ argument
79 ((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6)))
80 #define LONG_RUN_FAIL_MASK_SET(dst, src) \ argument
81 ((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5)))
82 #define RUN_FAIL_MASK_SET(dst, src) \ argument
83 ((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4)))
84 #define NOISE_FAIL_MASK_SET(dst, src) \ argument
85 ((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3)))
86 #define STUCK_OUT_MASK_SET(dst, src) \ argument
87 ((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2)))
88 #define SHUTDOWN_OFLO_MASK_SET(dst, src) \ argument
89 ((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1)))