66 	void __iomem *vaddr;  member
226          writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command()
227 	readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);  in SA5_submit_command()
243 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
244 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
249 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
250 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
263                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
264 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
269                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
270 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
279 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
280 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
284 				h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
285 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
308 		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);  in SA5_completed()
334 	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
337 		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);  in SA5_performant_completed()
341 		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
365 		readl(h->vaddr + SA5_INTR_STATUS);  in SA5_intr_pending()
380                 readl(h->vaddr + SA5_INTR_STATUS);  in SA5B_intr_pending()
391 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);  in SA5_performant_intr_pending()
400 	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_intr_pending()