Lines Matching refs:iadev
73 static void desc_dbg(IADEV *iadev);
576 IADEV *iadev; in ia_cbrVc_close() local
580 iadev = INPH_IA_DEV(vcc->dev); in ia_cbrVc_close()
581 iadev->NumEnabledCBR--; in ia_cbrVc_close()
582 SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize); in ia_cbrVc_close()
583 if (iadev->NumEnabledCBR == 0) { in ia_cbrVc_close()
584 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS); in ia_cbrVc_close()
588 for (i=0; i < iadev->CbrTotEntries; i++) in ia_cbrVc_close()
591 iadev->CbrRemEntries++; in ia_cbrVc_close()
600 static int ia_avail_descs(IADEV *iadev) { in ia_avail_descs() argument
602 ia_hack_tcq(iadev); in ia_avail_descs()
603 if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd) in ia_avail_descs()
604 tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2; in ia_avail_descs()
606 tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr - in ia_avail_descs()
607 iadev->ffL.tcq_st) / 2; in ia_avail_descs()
613 static int ia_que_tx (IADEV *iadev) { in ia_que_tx() argument
617 num_desc = ia_avail_descs(iadev); in ia_que_tx()
619 while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) { in ia_que_tx()
631 skb_queue_head(&iadev->tx_backlog, skb); in ia_que_tx()
638 static void ia_tx_poll (IADEV *iadev) { in ia_tx_poll() argument
644 ia_hack_tcq(iadev); in ia_tx_poll()
645 while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) { in ia_tx_poll()
683 ia_enque_head_rtn_q (&iadev->tx_return_q, rtne); in ia_tx_poll()
695 ia_que_tx(iadev); in ia_tx_poll()
700 static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val)
722 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
724 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
736 static u16 ia_eeprom_get (IADEV *iadev, u32 addr) in ia_eeprom_get() argument
760 static void ia_hw_type(IADEV *iadev) { argument
761 u_short memType = ia_eeprom_get(iadev, 25);
762 iadev->memType = memType;
764 iadev->num_tx_desc = IA_TX_BUF;
765 iadev->tx_buf_sz = IA_TX_BUF_SZ;
766 iadev->num_rx_desc = IA_RX_BUF;
767 iadev->rx_buf_sz = IA_RX_BUF_SZ;
770 iadev->num_tx_desc = IA_TX_BUF / 2;
772 iadev->num_tx_desc = IA_TX_BUF;
773 iadev->tx_buf_sz = IA_TX_BUF_SZ;
775 iadev->num_rx_desc = IA_RX_BUF / 2;
777 iadev->num_rx_desc = IA_RX_BUF;
778 iadev->rx_buf_sz = IA_RX_BUF_SZ;
782 iadev->num_tx_desc = IA_TX_BUF / 8;
784 iadev->num_tx_desc = IA_TX_BUF;
785 iadev->tx_buf_sz = IA_TX_BUF_SZ;
787 iadev->num_rx_desc = IA_RX_BUF / 8;
789 iadev->num_rx_desc = IA_RX_BUF;
790 iadev->rx_buf_sz = IA_RX_BUF_SZ;
792 iadev->rx_pkt_ram = TX_PACKET_RAM + (iadev->num_tx_desc * iadev->tx_buf_sz);
794 iadev->num_tx_desc, iadev->tx_buf_sz, iadev->num_rx_desc,
795 iadev->rx_buf_sz, iadev->rx_pkt_ram);)
799 iadev->phy_type = PHY_OC3C_S;
801 iadev->phy_type = PHY_UTP155;
803 iadev->phy_type = PHY_OC3C_M;
806 iadev->phy_type = memType & FE_MASK;
808 memType,iadev->phy_type);)
809 if (iadev->phy_type == FE_25MBIT_PHY)
810 iadev->LineRate = (u32)(((25600000/8)*26)/(27*53));
811 else if (iadev->phy_type == FE_DS3_PHY)
812 iadev->LineRate = (u32)(((44736000/8)*26)/(27*53));
813 else if (iadev->phy_type == FE_E3_PHY)
814 iadev->LineRate = (u32)(((34368000/8)*26)/(27*53));
816 iadev->LineRate = (u32)(ATM_OC3_PCR);
817 IF_INIT(printk("iadev->LineRate = %d \n", iadev->LineRate);)
831 static void ia_frontend_intr(struct iadev_priv *iadev) argument
835 if (iadev->phy_type & FE_25MBIT_PHY) {
836 status = ia_phy_read32(iadev, MB25_INTR_STATUS);
837 iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
838 } else if (iadev->phy_type & FE_DS3_PHY) {
839 ia_phy_read32(iadev, SUNI_DS3_FRM_INTR_STAT);
840 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
841 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
842 } else if (iadev->phy_type & FE_E3_PHY) {
843 ia_phy_read32(iadev, SUNI_E3_FRM_MAINT_INTR_IND);
844 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
845 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
847 status = ia_phy_read32(iadev, SUNI_RSOP_STATUS);
848 iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
852 iadev->carrier_detect ? "detected" : "lost signal");
855 static void ia_mb25_init(struct iadev_priv *iadev) argument
860 ia_phy_write32(iadev, MB25_MASTER_CTRL, MB25_MC_DRIC | MB25_MC_DREC);
861 ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);
863 iadev->carrier_detect =
864 (ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;
872 static void ia_phy_write(struct iadev_priv *iadev, argument
876 ia_phy_write32(iadev, regs->reg, regs->val);
881 static void ia_suni_pm7345_init_ds3(struct iadev_priv *iadev) argument
893 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
894 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
896 ia_phy_write(iadev, suni_ds3_init, ARRAY_SIZE(suni_ds3_init));
899 static void ia_suni_pm7345_init_e3(struct iadev_priv *iadev) argument
914 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
915 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
916 ia_phy_write(iadev, suni_e3_init, ARRAY_SIZE(suni_e3_init));
919 static void ia_suni_pm7345_init(struct iadev_priv *iadev) argument
957 if (iadev->phy_type & FE_DS3_PHY)
958 ia_suni_pm7345_init_ds3(iadev);
960 ia_suni_pm7345_init_e3(iadev);
962 ia_phy_write(iadev, suni_init, ARRAY_SIZE(suni_init));
964 ia_phy_write32(iadev, SUNI_CONFIG, ia_phy_read32(iadev, SUNI_CONFIG) &
1015 RAM_BASE*((iadev->mem)/(128 * 1024))
1017 IPHASE5575_FRAG_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1019 IPHASE5575_REASS_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1024 static void desc_dbg(IADEV *iadev) { argument
1030 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1032 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1033 readw(iadev->seg_ram+tcq_wr_ptr-2));
1034 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1035 iadev->ffL.tcq_rd);
1036 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1037 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1041 tmp = iadev->seg_ram+tcq_st_ptr;
1045 for(i=0; i <iadev->num_tx_desc; i++)
1046 printk("Desc_tbl[%d] = %d \n", i, iadev->desc_tbl[i].timestamp);
1055 IADEV *iadev;
1060 iadev = INPH_IA_DEV(dev);
1061 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1064 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1066 if (excpq_rd_ptr == *(u16*)(iadev->reass_reg + EXCP_Q_WR_PTR))
1069 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1070 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1073 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1074 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1075 writew( excpq_rd_ptr, iadev->reass_reg + EXCP_Q_RD_PTR);
1076 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1083 IADEV *iadev; local
1084 iadev = INPH_IA_DEV(dev);
1085 writew(desc, iadev->reass_ram+iadev->rfL.fdq_wr);
1086 iadev->rfL.fdq_wr +=2;
1087 if (iadev->rfL.fdq_wr > iadev->rfL.fdq_ed)
1088 iadev->rfL.fdq_wr = iadev->rfL.fdq_st;
1089 writew(iadev->rfL.fdq_wr, iadev->reass_reg+FREEQ_WR_PTR);
1095 IADEV *iadev; local
1105 iadev = INPH_IA_DEV(dev);
1106 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1112 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1114 iadev->reass_ram, iadev->rfL.pcq_rd, desc);
1116 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1118 if ( iadev->rfL.pcq_rd== iadev->rfL.pcq_ed)
1119 iadev->rfL.pcq_rd = iadev->rfL.pcq_st;
1121 iadev->rfL.pcq_rd += 2;
1122 writew(iadev->rfL.pcq_rd, iadev->reass_reg+PCQ_RD_PTR);
1127 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1130 if (!desc || (desc > iadev->num_rx_desc) ||
1131 ((buf_desc_ptr->vc_index & 0xffff) > iadev->num_vc)) {
1136 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1170 if (len > iadev->rx_buf_sz) {
1171 printk("Over %d bytes sdu received, dropped!!!\n", iadev->rx_buf_sz);
1185 skb_queue_tail(&iadev->rx_dma_q, skb);
1188 wr_ptr = iadev->rx_dle_q.write;
1189 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
1196 if(++wr_ptr == iadev->rx_dle_q.end)
1197 wr_ptr = iadev->rx_dle_q.start;
1198 iadev->rx_dle_q.write = wr_ptr;
1201 writel(1, iadev->dma+IPHASE5575_RX_COUNTER);
1210 IADEV *iadev; local
1214 iadev = INPH_IA_DEV(dev);
1215 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1225 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1230 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1232 iadev->rxing = 1;
1236 if (iadev->rxing) {
1237 iadev->rx_tmp_cnt = iadev->rx_pkt_cnt;
1238 iadev->rx_tmp_jif = jiffies;
1239 iadev->rxing = 0;
1241 else if ((time_after(jiffies, iadev->rx_tmp_jif + 50)) &&
1242 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1243 for (i = 1; i <= iadev->num_rx_desc; i++)
1246 writew( ~(RX_FREEQ_EMPT|RX_EXCP_RCVD),iadev->reass_reg+REASS_MASK_REG);
1247 iadev->rxing = 1;
1272 IADEV *iadev; local
1280 iadev = INPH_IA_DEV(dev);
1287 dle = iadev->rx_dle_q.read;
1288 dle_lp = readl(iadev->dma+IPHASE5575_RX_LIST_ADDR) & (sizeof(struct dle)*DLE_ENTRIES - 1);
1289 cur_dle = (struct dle*)(iadev->rx_dle_q.start + (dle_lp >> 4));
1293 skb = skb_dequeue(&iadev->rx_dma_q);
1310 dma_unmap_single(&iadev->pci->dev, iadev->rx_dle_q.write->sys_pkt_addr,
1331 if ((length > iadev->rx_buf_sz) || (length >
1351 iadev->rx_pkt_cnt++;
1354 if (++dle == iadev->rx_dle_q.end)
1355 dle = iadev->rx_dle_q.start;
1357 iadev->rx_dle_q.read = dle;
1361 if (!iadev->rxing) {
1362 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1364 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1366 iadev->reass_reg+REASS_MASK_REG);
1367 iadev->rxing++;
1375 IADEV *iadev; local
1381 iadev = INPH_IA_DEV(vcc->dev);
1383 if (iadev->phy_type & FE_25MBIT_PHY) {
1390 vc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;
1401 init_abr_vc(iadev, &srv_p);
1402 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1405 reass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;
1410 if (iadev->rx_open[vcc->vci])
1413 iadev->rx_open[vcc->vci] = vcc;
1419 IADEV *iadev; local
1430 iadev = INPH_IA_DEV(dev);
1434 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1435 &iadev->rx_dle_dma, GFP_KERNEL);
1440 iadev->rx_dle_q.start = (struct dle *)dle_addr;
1441 iadev->rx_dle_q.read = iadev->rx_dle_q.start;
1442 iadev->rx_dle_q.write = iadev->rx_dle_q.start;
1443 iadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1449 writel(iadev->rx_dle_dma & 0xfffff000,
1450 iadev->dma + IPHASE5575_RX_LIST_ADDR);
1452 iadev->dma+IPHASE5575_TX_LIST_ADDR,
1453 readl(iadev->dma + IPHASE5575_TX_LIST_ADDR));
1455 iadev->dma+IPHASE5575_RX_LIST_ADDR,
1456 readl(iadev->dma + IPHASE5575_RX_LIST_ADDR));)
1458 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1459 writew(0, iadev->reass_reg+MODE_REG);
1460 writew(RESET_REASS, iadev->reass_reg+REASS_COMMAND_REG);
1476 writew(RX_DESC_BASE >> 16, iadev->reass_reg+REASS_DESC_BASE);
1478 writew(iadev->rx_buf_sz, iadev->reass_reg+BUF_SIZE);
1481 iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;
1482 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1485 rx_pkt_start = iadev->rx_pkt_ram;
1486 for(i=1; i<=iadev->num_rx_desc; i++)
1492 rx_pkt_start += iadev->rx_buf_sz;
1495 i = FREE_BUF_DESC_Q*iadev->memSize;
1496 writew(i >> 16, iadev->reass_reg+REASS_QUEUE_BASE);
1497 writew(i, iadev->reass_reg+FREEQ_ST_ADR);
1498 writew(i+iadev->num_rx_desc*sizeof(u_short),
1499 iadev->reass_reg+FREEQ_ED_ADR);
1500 writew(i, iadev->reass_reg+FREEQ_RD_PTR);
1501 writew(i+iadev->num_rx_desc*sizeof(u_short),
1502 iadev->reass_reg+FREEQ_WR_PTR);
1504 freeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR);
1505 freeq_start = (u_short *)(iadev->reass_ram+freeq_st_adr);
1506 for(i=1; i<=iadev->num_rx_desc; i++)
1513 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1514 writew(i, iadev->reass_reg+PCQ_ST_ADR);
1515 writew(i+iadev->num_vc*sizeof(u_short), iadev->reass_reg+PCQ_ED_ADR);
1516 writew(i, iadev->reass_reg+PCQ_RD_PTR);
1517 writew(i, iadev->reass_reg+PCQ_WR_PTR);
1520 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1521 writew(i, iadev->reass_reg+EXCP_Q_ST_ADR);
1523 iadev->reass_reg+EXCP_Q_ED_ADR);
1524 writew(i, iadev->reass_reg+EXCP_Q_RD_PTR);
1525 writew(i, iadev->reass_reg+EXCP_Q_WR_PTR);
1528 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1529 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1530 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1531 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1532 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1533 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1534 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1535 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1538 iadev->rfL.pcq_st, iadev->rfL.pcq_ed, iadev->rfL.pcq_rd,
1539 iadev->rfL.pcq_wr);)
1549 i = REASS_TABLE * iadev->memSize;
1550 writew((i >> 3), iadev->reass_reg+REASS_TABLE_BASE);
1552 reass_table = (u16 *)(iadev->reass_ram+i);
1553 j = REASS_TABLE_SZ * iadev->memSize;
1558 while (i != iadev->num_vc) {
1562 i = RX_VC_TABLE * iadev->memSize;
1563 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1564 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
1565 j = RX_VC_TABLE_SZ * iadev->memSize;
1577 i = ABR_VC_TABLE * iadev->memSize;
1578 writew(i >> 3, iadev->reass_reg+ABR_LKUP_BASE);
1580 i = ABR_VC_TABLE * iadev->memSize;
1581 abr_vc_table = (struct abr_vc_table *)(iadev->reass_ram+i);
1582 j = REASS_TABLE_SZ * iadev->memSize;
1593 writew(0xff00, iadev->reass_reg+VP_FILTER);
1594 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1595 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1601 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1606 writew(i, iadev->reass_reg+TMOUT_RANGE);
1609 for(i=0; i<iadev->num_tx_desc;i++)
1610 iadev->desc_tbl[i].timestamp = 0;
1613 readw(iadev->reass_reg+REASS_INTR_STATUS_REG);
1616 writew(~(RX_FREEQ_EMPT|RX_PKT_RCVD), iadev->reass_reg+REASS_MASK_REG);
1618 skb_queue_head_init(&iadev->rx_dma_q);
1619 iadev->rx_free_desc_qhead = NULL;
1621 iadev->rx_open = kzalloc(4 * iadev->num_vc, GFP_KERNEL);
1622 if (!iadev->rx_open) {
1628 iadev->rxing = 1;
1629 iadev->rx_pkt_cnt = 0;
1631 writew(R_ONLINE, iadev->reass_reg+MODE_REG);
1635 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
1636 iadev->rx_dle_dma);
1659 IADEV *iadev; local
1663 iadev = INPH_IA_DEV(dev);
1665 status = readl(iadev->seg_reg+SEG_INTR_STATUS_REG);
1669 spin_lock_irqsave(&iadev->tx_lock, flags);
1670 ia_tx_poll(iadev);
1671 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1672 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
1673 if (iadev->close_pending)
1674 wake_up(&iadev->close_wait);
1684 IADEV *iadev; local
1692 iadev = INPH_IA_DEV(dev);
1693 spin_lock_irqsave(&iadev->tx_lock, flags);
1694 dle = iadev->tx_dle_q.read;
1695 dle_lp = readl(iadev->dma+IPHASE5575_TX_LIST_ADDR) &
1697 cur_dle = (struct dle*)(iadev->tx_dle_q.start + (dle_lp >> 4));
1701 skb = skb_dequeue(&iadev->tx_dma_q);
1705 if (!((dle - iadev->tx_dle_q.start)%(2*sizeof(struct dle)))) {
1706 dma_unmap_single(&iadev->pci->dev, dle->sys_pkt_addr, skb->len,
1712 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1720 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1724 if (vcc->qos.txtp.pcr >= iadev->rate_limit) {
1738 if (++dle == iadev->tx_dle_q.end)
1739 dle = iadev->tx_dle_q.start;
1741 iadev->tx_dle_q.read = dle;
1742 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1748 IADEV *iadev; local
1754 iadev = INPH_IA_DEV(vcc->dev);
1756 if (iadev->phy_type & FE_25MBIT_PHY) {
1769 (iadev->tx_buf_sz - sizeof(struct cpcs_trailer))){
1771 vcc->qos.txtp.max_sdu,iadev->tx_buf_sz);
1781 vcc->qos.txtp.pcr = iadev->LineRate;
1783 vcc->qos.txtp.pcr = iadev->LineRate;
1786 if (vcc->qos.txtp.pcr > iadev->LineRate)
1787 vcc->qos.txtp.pcr = iadev->LineRate;
1790 if (ia_vcc->pcr > (iadev->LineRate / 6) ) ia_vcc->ltimeout = HZ / 10;
1791 else if (ia_vcc->pcr > (iadev->LineRate / 130)) ia_vcc->ltimeout = HZ;
1794 if (ia_vcc->pcr < iadev->rate_limit)
1796 if (ia_vcc->pcr < iadev->rate_limit) {
1811 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
1812 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
1831 vc->acr = cellrate_to_float(iadev->LineRate);
1840 init_abr_vc(iadev, &srv_p);
1844 int tmpsum = iadev->sum_mcr+iadev->sum_cbr+vcc->qos.txtp.min_pcr;
1845 if (tmpsum > iadev->LineRate)
1848 iadev->sum_mcr += vcc->qos.txtp.min_pcr;
1873 ia_open_abr_vc(iadev, &srv_p, vcc, 1);
1875 if (iadev->phy_type & FE_25MBIT_PHY) {
1879 if (vcc->qos.txtp.max_pcr > iadev->LineRate) {
1885 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1892 iadev->testTable[vcc->vci]->vc_status |= VC_ACTIVE;
1900 IADEV *iadev; local
1914 iadev = INPH_IA_DEV(dev);
1915 spin_lock_init(&iadev->tx_lock);
1918 readw(iadev->seg_reg+SEG_MASK_REG));)
1921 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1922 &iadev->tx_dle_dma, GFP_KERNEL);
1927 iadev->tx_dle_q.start = (struct dle*)dle_addr;
1928 iadev->tx_dle_q.read = iadev->tx_dle_q.start;
1929 iadev->tx_dle_q.write = iadev->tx_dle_q.start;
1930 iadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1933 writel(iadev->tx_dle_dma & 0xfffff000,
1934 iadev->dma + IPHASE5575_TX_LIST_ADDR);
1935 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1936 writew(0, iadev->seg_reg+MODE_REG_0);
1937 writew(RESET_SEG, iadev->seg_reg+SEG_COMMAND_REG);
1938 iadev->MAIN_VC_TABLE_ADDR = iadev->seg_ram+MAIN_VC_TABLE*iadev->memSize;
1939 iadev->EXT_VC_TABLE_ADDR = iadev->seg_ram+EXT_VC_TABLE*iadev->memSize;
1940 iadev->ABR_SCHED_TABLE_ADDR=iadev->seg_ram+ABR_SCHED_TABLE*iadev->memSize;
1962 writew(TX_DESC_BASE, iadev->seg_reg+SEG_DESC_BASE);
1965 buf_desc_ptr =(struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE);
1969 for(i=1; i<=iadev->num_tx_desc; i++)
1976 tx_pkt_start += iadev->tx_buf_sz;
1978 iadev->tx_buf = kmalloc(iadev->num_tx_desc*sizeof(struct cpcs_trailer_desc), GFP_KERNEL);
1979 if (!iadev->tx_buf) {
1983 for (i= 0; i< iadev->num_tx_desc; i++)
1992 iadev->tx_buf[i].cpcs = cpcs;
1993 iadev->tx_buf[i].dma_addr = dma_map_single(&iadev->pci->dev,
1998 iadev->desc_tbl = kmalloc(iadev->num_tx_desc *
2000 if (!iadev->desc_tbl) {
2006 i = TX_COMP_Q * iadev->memSize;
2007 writew(i >> 16, iadev->seg_reg+SEG_QUEUE_BASE);
2010 writew(i, iadev->seg_reg+TCQ_ST_ADR);
2011 writew(i, iadev->seg_reg+TCQ_RD_PTR);
2012 writew(i+iadev->num_tx_desc*sizeof(u_short),iadev->seg_reg+TCQ_WR_PTR);
2013 iadev->host_tcq_wr = i + iadev->num_tx_desc*sizeof(u_short);
2014 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2015 iadev->seg_reg+TCQ_ED_ADR);
2017 tcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR);
2018 tcq_start = (u_short *)(iadev->seg_ram+tcq_st_adr);
2019 for(i=1; i<=iadev->num_tx_desc; i++)
2026 i = PKT_RDY_Q * iadev->memSize;
2027 writew(i, iadev->seg_reg+PRQ_ST_ADR);
2028 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2029 iadev->seg_reg+PRQ_ED_ADR);
2030 writew(i, iadev->seg_reg+PRQ_RD_PTR);
2031 writew(i, iadev->seg_reg+PRQ_WR_PTR);
2034 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2035 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2036 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2038 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2039 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2040 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2044 prq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR);
2045 prq_start = (u_short *)(iadev->seg_ram+prq_st_adr);
2046 for(i=1; i<=iadev->num_tx_desc; i++)
2054 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2056 tmp16 = (iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize)>>17;
2058 writew(tmp16,iadev->seg_reg+CBR_PTR_BASE);
2062 readw(iadev->seg_reg+CBR_PTR_BASE));)
2063 tmp16 = (CBR_SCHED_TABLE*iadev->memSize) >> 1;
2064 writew(tmp16, iadev->seg_reg+CBR_TAB_BEG);
2066 readw(iadev->seg_reg+CBR_TAB_BEG));)
2067 writew(tmp16, iadev->seg_reg+CBR_TAB_END+1); // CBR_PTR;
2068 tmp16 = (CBR_SCHED_TABLE*iadev->memSize + iadev->num_vc*6 - 2) >> 1;
2069 writew(tmp16, iadev->seg_reg+CBR_TAB_END);
2071 iadev->seg_reg, readw(iadev->seg_reg+CBR_PTR_BASE));)
2073 readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
2074 readw(iadev->seg_reg+CBR_TAB_END+1));)
2077 memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize,
2078 0, iadev->num_vc*6);
2079 iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;
2080 iadev->CbrEntryPt = 0;
2081 iadev->Granularity = MAX_ATM_155 / iadev->CbrTotEntries;
2082 iadev->NumEnabledCBR = 0;
2095 while (i != iadev->num_vc) {
2100 i = MAIN_VC_TABLE * iadev->memSize;
2101 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2102 i = EXT_VC_TABLE * iadev->memSize;
2103 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2104 i = UBR_SCHED_TABLE * iadev->memSize;
2105 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2106 i = UBR_WAIT_Q * iadev->memSize;
2107 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2108 memset((caddr_t)(iadev->seg_ram+UBR_SCHED_TABLE*iadev->memSize),
2109 0, iadev->num_vc*8);
2118 i = ABR_SCHED_TABLE * iadev->memSize;
2119 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2120 i = ABR_WAIT_Q * iadev->memSize;
2121 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2123 i = ABR_SCHED_TABLE*iadev->memSize;
2124 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2125 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
2126 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
2127 iadev->testTable = kmalloc(sizeof(long)*iadev->num_vc, GFP_KERNEL);
2128 if (!iadev->testTable) {
2132 for(i=0; i<iadev->num_vc; i++)
2136 iadev->testTable[i] = kmalloc(sizeof(struct testTable_t),
2138 if (!iadev->testTable[i])
2140 iadev->testTable[i]->lastTime = 0;
2141 iadev->testTable[i]->fract = 0;
2142 iadev->testTable[i]->vc_status = VC_UBR;
2150 if (iadev->phy_type & FE_25MBIT_PHY) {
2151 writew(RATE25, iadev->seg_reg+MAXRATE);
2152 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2155 writew(cellrate_to_float(iadev->LineRate),iadev->seg_reg+MAXRATE);
2156 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2159 writew(0, iadev->seg_reg+IDLEHEADHI);
2160 writew(0, iadev->seg_reg+IDLEHEADLO);
2163 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2165 iadev->close_pending = 0;
2166 init_waitqueue_head(&iadev->close_wait);
2167 init_waitqueue_head(&iadev->timeout_wait);
2168 skb_queue_head_init(&iadev->tx_dma_q);
2169 ia_init_rtn_q(&iadev->tx_return_q);
2172 writew(RM_TYPE_4_0, iadev->seg_reg+RM_TYPE);
2173 skb_queue_head_init (&iadev->tx_backlog);
2176 writew(MODE_REG_1_VAL, iadev->seg_reg+MODE_REG_1);
2179 writew(T_ONLINE, iadev->seg_reg+MODE_REG_0);
2182 readw(iadev->seg_reg+SEG_INTR_STATUS_REG);
2185 writew(~(TRANSMIT_DONE | TCQ_NOT_EMPTY), iadev->seg_reg+SEG_MASK_REG);
2186 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2187 iadev->tx_pkt_cnt = 0;
2188 iadev->rate_limit = iadev->LineRate / 3;
2194 kfree(iadev->testTable[i]);
2195 kfree(iadev->testTable);
2197 kfree(iadev->desc_tbl);
2199 i = iadev->num_tx_desc;
2202 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2204 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2208 kfree(iadev->tx_buf);
2210 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2211 iadev->tx_dle_dma);
2219 IADEV *iadev; local
2224 iadev = INPH_IA_DEV(dev);
2225 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2238 writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2249 writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2255 ia_frontend_intr(iadev);
2266 IADEV *iadev; local
2271 iadev = INPH_IA_DEV(dev);
2273 iadev->reg+IPHASE5575_MAC1)));
2274 mac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2)));
2286 IADEV *iadev; local
2290 iadev = INPH_IA_DEV(dev);
2292 if ((error = pci_read_config_dword(iadev->pci,
2295 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2297 if ((error = pci_write_config_dword(iadev->pci,
2307 IADEV *iadev; local
2321 iadev = INPH_IA_DEV(dev);
2322 real_base = pci_resource_start (iadev->pci, 0);
2323 iadev->irq = iadev->pci->irq;
2325 error = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);
2332 dev->number, iadev->pci->revision, real_base, iadev->irq);)
2336 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2338 if (iadev->pci_map_size == 0x100000){
2339 iadev->num_vc = 4096;
2341 iadev->memSize = 4;
2343 else if (iadev->pci_map_size == 0x40000) {
2344 iadev->num_vc = 1024;
2345 iadev->memSize = 1;
2348 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2351 IF_INIT(printk (DEV_LABEL "map size: %i\n", iadev->pci_map_size);)
2354 pci_set_master(iadev->pci);
2362 base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
2371 dev->number, iadev->pci->revision, base, iadev->irq);)
2374 iadev->mem = iadev->pci_map_size /2;
2375 iadev->real_base = real_base;
2376 iadev->base = base;
2379 iadev->reg = base + REG_BASE;
2381 iadev->seg_reg = base + SEG_BASE;
2383 iadev->reass_reg = base + REASS_BASE;
2385 iadev->phy = base + PHY_BASE;
2386 iadev->dma = base + PHY_BASE;
2388 iadev->ram = base + ACTUAL_RAM_BASE;
2389 iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE;
2390 iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE;
2394 iadev->reg,iadev->seg_reg,iadev->reass_reg,
2395 iadev->phy, iadev->ram, iadev->seg_ram,
2396 iadev->reass_ram);)
2401 iounmap(iadev->base);
2411 iounmap(iadev->base);
2418 static void ia_update_stats(IADEV *iadev) { argument
2419 if (!iadev->carrier_detect)
2421 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2422 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2423 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2424 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2425 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2426 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2471 static void ia_free_tx(IADEV *iadev) argument
2475 kfree(iadev->desc_tbl);
2476 for (i = 0; i < iadev->num_vc; i++)
2477 kfree(iadev->testTable[i]);
2478 kfree(iadev->testTable);
2479 for (i = 0; i < iadev->num_tx_desc; i++) {
2480 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2482 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2486 kfree(iadev->tx_buf);
2487 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2488 iadev->tx_dle_dma);
2491 static void ia_free_rx(IADEV *iadev) argument
2493 kfree(iadev->rx_open);
2494 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
2495 iadev->rx_dle_dma);
2500 IADEV *iadev; local
2505 iadev = INPH_IA_DEV(dev);
2506 if (request_irq(iadev->irq, &ia_int, IRQF_SHARED, DEV_LABEL, dev)) {
2508 dev->number, iadev->irq);
2514 if ((error = pci_write_config_word(iadev->pci,
2529 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2530 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2546 writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2549 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));
2551 readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));)
2553 ia_hw_type(iadev);
2561 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2562 writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2564 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2572 if (iadev->phy_type & FE_25MBIT_PHY)
2573 ia_mb25_init(iadev);
2574 else if (iadev->phy_type & (FE_DS3_PHY | FE_E3_PHY))
2575 ia_suni_pm7345_init(iadev);
2586 ia_frontend_intr(iadev);
2591 ia_free_rx(iadev);
2593 ia_free_tx(iadev);
2595 free_irq(iadev->irq, dev);
2604 IADEV *iadev; local
2610 iadev = INPH_IA_DEV(vcc->dev);
2620 iadev->close_pending++;
2621 prepare_to_wait(&iadev->timeout_wait, &wait, TASK_UNINTERRUPTIBLE);
2623 finish_wait(&iadev->timeout_wait, &wait);
2624 spin_lock_irqsave(&iadev->tx_lock, flags);
2625 while((skb = skb_dequeue(&iadev->tx_backlog))) {
2634 skb_queue_tail(&iadev->tx_backlog, skb);
2639 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2640 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2641 spin_lock_irqsave(&iadev->tx_lock, flags);
2642 iadev->close_pending--;
2643 iadev->testTable[vcc->vci]->lastTime = 0;
2644 iadev->testTable[vcc->vci]->fract = 0;
2645 iadev->testTable[vcc->vci]->vc_status = VC_UBR;
2648 iadev->sum_mcr -= vcc->qos.txtp.min_pcr;
2652 iadev->sum_mcr -= ia_vcc->NumCbrEntry*iadev->Granularity;
2655 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2660 vc_table = (u16 *)(iadev->reass_ram+REASS_TABLE*iadev->memSize);
2664 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
2669 (iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);
2676 iadev->rx_open[vcc->vci] = NULL;
2748 IADEV *iadev; local
2760 iadev = ia_dev[board];
2767 if (copy_to_user(ia_cmds.buf, iadev, sizeof(IADEV)))
2775 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2783 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2800 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2803 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2817 desc_dbg(iadev);
2824 printk("skb = 0x%lx\n", (long)skb_peek(&iadev->tx_backlog));
2825 printk("rtn_q: 0x%lx\n",(long)ia_deque_rtn_q(&iadev->tx_return_q));
2846 for (i = 1; i <= iadev->num_rx_desc; i++)
2849 iadev->reass_reg+REASS_MASK_REG);
2850 iadev->rxing = 1;
2857 ia_frontend_intr(iadev);
2895 IADEV *iadev; local
2904 iadev = INPH_IA_DEV(vcc->dev);
2915 if (skb->len > iadev->tx_buf_sz - 8) {
2936 desc = get_desc (iadev, iavcc);
2942 if ((desc == 0) || (desc > iadev->num_tx_desc))
2961 iadev->desc_tbl[desc-1].iavcc = iavcc;
2962 iadev->desc_tbl[desc-1].txskb = skb;
2965 iadev->ffL.tcq_rd += 2;
2966 if (iadev->ffL.tcq_rd > iadev->ffL.tcq_ed)
2967 iadev->ffL.tcq_rd = iadev->ffL.tcq_st;
2968 writew(iadev->ffL.tcq_rd, iadev->seg_reg+TCQ_RD_PTR);
2973 *(u16*)(iadev->seg_ram+iadev->ffL.prq_wr) = desc;
2975 iadev->ffL.prq_wr += 2;
2976 if (iadev->ffL.prq_wr > iadev->ffL.prq_ed)
2977 iadev->ffL.prq_wr = iadev->ffL.prq_st;
2986 trailer = iadev->tx_buf[desc-1].cpcs;
3001 buf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;
3005 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
3010 clear_lockup (vcc, iadev);
3013 wr_ptr = iadev->tx_dle_q.write;
3015 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
3030 if (++wr_ptr == iadev->tx_dle_q.end)
3031 wr_ptr = iadev->tx_dle_q.start;
3034 wr_ptr->sys_pkt_addr = iadev->tx_buf[desc-1].dma_addr;
3040 wr_ptr->prq_wr_ptr_data = iadev->ffL.prq_wr;
3043 if (++wr_ptr == iadev->tx_dle_q.end)
3044 wr_ptr = iadev->tx_dle_q.start;
3046 iadev->tx_dle_q.write = wr_ptr;
3048 skb_queue_tail(&iadev->tx_dma_q, skb);
3051 iadev->tx_pkt_cnt++;
3053 writel(2, iadev->dma+IPHASE5575_TX_COUNTER);
3076 IADEV *iadev; local
3079 iadev = INPH_IA_DEV(vcc->dev);
3080 if ((!skb)||(skb->len>(iadev->tx_buf_sz-sizeof(struct cpcs_trailer))))
3087 spin_lock_irqsave(&iadev->tx_lock, flags);
3090 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3095 if (skb_peek(&iadev->tx_backlog)) {
3096 skb_queue_tail(&iadev->tx_backlog, skb);
3100 skb_queue_tail(&iadev->tx_backlog, skb);
3103 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3112 IADEV *iadev = INPH_IA_DEV(dev); local
3114 if (iadev->phy_type == FE_25MBIT_PHY) {
3118 if (iadev->phy_type == FE_DS3_PHY)
3120 else if (iadev->phy_type == FE_E3_PHY)
3122 else if (iadev->phy_type == FE_UTP_OPTION)
3127 if (iadev->pci_map_size == 0x40000)
3132 if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_1M)
3134 else if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_512K)
3151 iadev->num_tx_desc, iadev->tx_buf_sz,
3152 iadev->num_rx_desc, iadev->rx_buf_sz,
3153 iadev->rx_pkt_cnt, iadev->tx_pkt_cnt,
3154 iadev->rx_cell_cnt, iadev->tx_cell_cnt,
3155 iadev->drop_rxcell, iadev->drop_rxpkt);
3177 IADEV *iadev; local
3180 iadev = kzalloc(sizeof(*iadev), GFP_KERNEL);
3181 if (!iadev) {
3186 iadev->pci = pdev;
3199 dev->dev_data = iadev;
3202 iadev->LineRate);)
3206 ia_dev[iadev_count] = iadev;
3219 iadev->next_board = ia_boards;
3229 kfree(iadev);
3237 IADEV *iadev = INPH_IA_DEV(dev); local
3248 free_irq(iadev->irq, dev);
3255 iounmap(iadev->base);
3258 ia_free_rx(iadev);
3259 ia_free_tx(iadev);
3261 kfree(iadev);