Lines Matching refs:dev
370 static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) { in wr_regl() argument
371 outl (cpu_to_le32 (data), dev->iobase + reg); in wr_regl()
374 static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) { in rd_regl() argument
375 return le32_to_cpu (inl (dev->iobase + reg)); in rd_regl()
378 static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) { in wr_regw() argument
379 outw (cpu_to_le16 (data), dev->iobase + reg); in wr_regw()
382 static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) { in rd_regw() argument
383 return le16_to_cpu (inw (dev->iobase + reg)); in rd_regw()
386 static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) { in wrs_regb() argument
387 outsb (dev->iobase + reg, addr, len); in wrs_regb()
390 static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) { in rds_regb() argument
391 insb (dev->iobase + reg, addr, len); in rds_regb()
397 static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) { in wr_mem() argument
399 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW)); in wr_mem()
400 wr_regl (dev, MEMORY_PORT_OFF, data); in wr_mem()
403 static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) { in rd_mem() argument
405 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW)); in rd_mem()
406 return rd_regl (dev, MEMORY_PORT_OFF); in rd_mem()
409 static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) { in wr_framer() argument
410 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000); in wr_framer()
411 wr_regl (dev, MEMORY_PORT_OFF, data); in wr_framer()
414 static inline u32 rd_framer (const hrz_dev * dev, u32 addr) { in rd_framer() argument
415 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000); in rd_framer()
416 return rd_regl (dev, MEMORY_PORT_OFF); in rd_framer()
423 static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) { in FLUSH_RX_CHANNEL() argument
424 wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel); in FLUSH_RX_CHANNEL()
428 static void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) { in WAIT_FLUSH_RX_COMPLETE() argument
429 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL) in WAIT_FLUSH_RX_COMPLETE()
434 static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) { in SELECT_RX_CHANNEL() argument
435 wr_regw (dev, RX_CHANNEL_PORT_OFF, channel); in SELECT_RX_CHANNEL()
439 static void WAIT_UPDATE_COMPLETE (hrz_dev * dev) { in WAIT_UPDATE_COMPLETE() argument
440 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS) in WAIT_UPDATE_COMPLETE()
447 static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) { in SELECT_TX_CHANNEL() argument
448 wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel); in SELECT_TX_CHANNEL()
454 static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) { in update_tx_channel_config() argument
455 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF, in update_tx_channel_config()
457 wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value); in update_tx_channel_config()
479 static inline void dump_regs (hrz_dev * dev) { in dump_regs() argument
481 PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG)); in dump_regs()
482 PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF)); in dump_regs()
483 PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF)); in dump_regs()
484 PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF)); in dump_regs()
485 PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF)); in dump_regs()
486 PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF)); in dump_regs()
488 (void) dev; in dump_regs()
493 static inline void dump_framer (hrz_dev * dev) { in dump_framer() argument
498 PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i)); in dump_framer()
501 (void) dev; in dump_framer()
586 static int make_rate (const hrz_dev * dev, u32 c, rounding r, in make_rate() argument
590 const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ; in make_rate()
693 static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol, in make_rate_with_tolerance() argument
704 if (make_rate (dev, c, round_nearest, bit_pattern, actual)) in make_rate_with_tolerance()
713 return make_rate (dev, c, r, bit_pattern, actual); in make_rate_with_tolerance()
718 static int hrz_open_rx (hrz_dev * dev, u16 channel) { in hrz_open_rx() argument
731 spin_lock_irqsave (&dev->mem_lock, flags); in hrz_open_rx()
732 channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK; in hrz_open_rx()
733 spin_unlock_irqrestore (&dev->mem_lock, flags); in hrz_open_rx()
742 if (dev->noof_spare_buffers) { in hrz_open_rx()
743 buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers]; in hrz_open_rx()
758 spin_lock_irqsave (&dev->mem_lock, flags); in hrz_open_rx()
760 wr_mem (dev, &rx_desc->wr_buf_type, in hrz_open_rx()
763 wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr); in hrz_open_rx()
765 spin_unlock_irqrestore (&dev->mem_lock, flags); in hrz_open_rx()
794 static void hrz_close_rx (hrz_dev * dev, u16 vc) { in hrz_close_rx() argument
805 spin_lock_irqsave (&dev->mem_lock, flags); in hrz_close_rx()
806 value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK; in hrz_close_rx()
807 spin_unlock_irqrestore (&dev->mem_lock, flags); in hrz_close_rx()
817 spin_lock_irqsave (&dev->mem_lock, flags); in hrz_close_rx()
820 wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED); in hrz_close_rx()
822 if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED) in hrz_close_rx()
829 spin_unlock_irqrestore (&dev->mem_lock, flags); in hrz_close_rx()
833 WAIT_FLUSH_RX_COMPLETE(dev); in hrz_close_rx()
863 SELECT_RX_CHANNEL (dev, other); in hrz_close_rx()
864 WAIT_UPDATE_COMPLETE (dev); in hrz_close_rx()
866 r1 = rd_mem (dev, &rx_desc->rd_buf_type); in hrz_close_rx()
871 SELECT_RX_CHANNEL (dev, vc); in hrz_close_rx()
872 WAIT_UPDATE_COMPLETE (dev); in hrz_close_rx()
876 FLUSH_RX_CHANNEL (dev, vc); in hrz_close_rx()
877 WAIT_FLUSH_RX_COMPLETE (dev); in hrz_close_rx()
881 SELECT_RX_CHANNEL (dev, other); in hrz_close_rx()
882 WAIT_UPDATE_COMPLETE (dev); in hrz_close_rx()
884 r2 = rd_mem (dev, &rx_desc->rd_buf_type); in hrz_close_rx()
889 dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1; in hrz_close_rx()
896 rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)]; in hrz_close_rx()
897 rx_q_entry * rd_ptr = dev->rx_q_entry; in hrz_close_rx()
902 u32 x = rd_mem (dev, (HDW *) rd_ptr); in hrz_close_rx()
909 wr_mem (dev, (HDW *) rd_ptr, x); in hrz_close_rx()
912 if (rd_ptr == dev->rx_q_wrap) in hrz_close_rx()
913 rd_ptr = dev->rx_q_reset; in hrz_close_rx()
920 spin_unlock_irqrestore (&dev->mem_lock, flags); in hrz_close_rx()
933 static void rx_schedule (hrz_dev * dev, int irq) { in rx_schedule() argument
942 rx_bytes = dev->rx_bytes; in rx_schedule()
946 while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) { in rx_schedule()
950 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); in rx_schedule()
951 clear_bit (rx_busy, &dev->flags); in rx_schedule()
952 hrz_kfree_skb (dev->rx_skb); in rx_schedule()
970 dev->rx_bytes = 0; in rx_schedule()
973 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT; in rx_schedule()
980 unsigned int rx_regions = dev->rx_regions; in rx_schedule()
988 dev->rx_addr = dev->rx_iovec->iov_base; in rx_schedule()
989 rx_bytes = dev->rx_iovec->iov_len; in rx_schedule()
990 ++dev->rx_iovec; in rx_schedule()
991 dev->rx_regions = rx_regions - 1; in rx_schedule()
999 dev->rx_bytes = 0; in rx_schedule()
1002 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT; in rx_schedule()
1009 struct sk_buff * skb = dev->rx_skb; in rx_schedule()
1012 FLUSH_RX_CHANNEL (dev, dev->rx_channel); in rx_schedule()
1014 dump_skb ("<<<", dev->rx_channel, skb); in rx_schedule()
1033 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); in rx_schedule()
1034 rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes); in rx_schedule()
1036 wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr)); in rx_schedule()
1037 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes); in rx_schedule()
1039 dev->rx_addr += rx_bytes; in rx_schedule()
1042 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); in rx_schedule()
1044 YELLOW_LED_ON(dev); in rx_schedule()
1045 clear_bit (rx_busy, &dev->flags); in rx_schedule()
1046 PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev); in rx_schedule()
1052 return rx_schedule (dev, 0); in rx_schedule()
1064 static void rx_bus_master_complete_handler (hrz_dev * dev) { in rx_bus_master_complete_handler() argument
1065 if (test_bit (rx_busy, &dev->flags)) { in rx_bus_master_complete_handler()
1066 rx_schedule (dev, 1); in rx_bus_master_complete_handler()
1070 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); in rx_bus_master_complete_handler()
1077 static int tx_hold (hrz_dev * dev) { in tx_hold() argument
1078 PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags); in tx_hold()
1079 wait_event_interruptible(dev->tx_queue, (!test_and_set_bit(tx_busy, &dev->flags))); in tx_hold()
1080 PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags); in tx_hold()
1083 PRINTD (DBG_TX, "set tx_busy for dev %p", dev); in tx_hold()
1089 static inline void tx_release (hrz_dev * dev) { in tx_release() argument
1090 clear_bit (tx_busy, &dev->flags); in tx_release()
1091 PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev); in tx_release()
1092 wake_up_interruptible (&dev->tx_queue); in tx_release()
1097 static void tx_schedule (hrz_dev * const dev, int irq) { in tx_schedule() argument
1108 tx_bytes = dev->tx_bytes; in tx_schedule()
1112 while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) { in tx_schedule()
1116 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); in tx_schedule()
1117 tx_release (dev); in tx_schedule()
1118 hrz_kfree_skb (dev->tx_skb); in tx_schedule()
1126 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) { in tx_schedule()
1132 if (!dev->tx_iovec) { in tx_schedule()
1136 dev->tx_bytes = 0; in tx_schedule()
1139 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT; in tx_schedule()
1145 unsigned int tx_regions = dev->tx_regions; in tx_schedule()
1149 dev->tx_addr = dev->tx_iovec->iov_base; in tx_schedule()
1150 tx_bytes = dev->tx_iovec->iov_len; in tx_schedule()
1151 ++dev->tx_iovec; in tx_schedule()
1152 dev->tx_regions = tx_regions - 1; in tx_schedule()
1154 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) { in tx_schedule()
1160 dev->tx_bytes = 0; in tx_schedule()
1163 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT; in tx_schedule()
1169 struct sk_buff * skb = dev->tx_skb; in tx_schedule()
1170 dev->tx_iovec = NULL; in tx_schedule()
1184 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); in tx_schedule()
1185 wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes); in tx_schedule()
1187 wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len)); in tx_schedule()
1189 wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr)); in tx_schedule()
1191 wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len)); in tx_schedule()
1192 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, in tx_schedule()
1197 dev->tx_addr += tx_bytes; in tx_schedule()
1200 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); in tx_schedule()
1201 YELLOW_LED_ON(dev); in tx_schedule()
1202 tx_release (dev); in tx_schedule()
1208 return tx_schedule (dev, 0); in tx_schedule()
1220 static void tx_bus_master_complete_handler (hrz_dev * dev) { in tx_bus_master_complete_handler() argument
1221 if (test_bit (tx_busy, &dev->flags)) { in tx_bus_master_complete_handler()
1222 tx_schedule (dev, 1); in tx_bus_master_complete_handler()
1226 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0); in tx_bus_master_complete_handler()
1234 static u32 rx_queue_entry_next (hrz_dev * dev) { in rx_queue_entry_next() argument
1236 spin_lock (&dev->mem_lock); in rx_queue_entry_next()
1237 rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry); in rx_queue_entry_next()
1238 if (dev->rx_q_entry == dev->rx_q_wrap) in rx_queue_entry_next()
1239 dev->rx_q_entry = dev->rx_q_reset; in rx_queue_entry_next()
1241 dev->rx_q_entry++; in rx_queue_entry_next()
1242 wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset); in rx_queue_entry_next()
1243 spin_unlock (&dev->mem_lock); in rx_queue_entry_next()
1250 static void rx_data_av_handler (hrz_dev * dev) { in rx_data_av_handler() argument
1259 if (test_and_set_bit (rx_busy, &dev->flags)) { in rx_data_av_handler()
1263 PRINTD (DBG_RX, "set rx_busy for dev %p", dev); in rx_data_av_handler()
1266 YELLOW_LED_OFF(dev); in rx_data_av_handler()
1268 rx_queue_entry = rx_queue_entry_next (dev); in rx_data_av_handler()
1273 WAIT_FLUSH_RX_COMPLETE (dev); in rx_data_av_handler()
1275 SELECT_RX_CHANNEL (dev, rx_channel); in rx_data_av_handler()
1295 atm_vcc = dev->rxer[rx_channel]; in rx_data_av_handler()
1308 dev->rx_skb = skb; in rx_data_av_handler()
1310 dev->rx_channel = rx_channel; in rx_data_av_handler()
1319 dev->rx_bytes = rx_len; in rx_data_av_handler()
1320 dev->rx_addr = skb->data; in rx_data_av_handler()
1325 rx_schedule (dev, 0); in rx_data_av_handler()
1352 YELLOW_LED_ON(dev); in rx_data_av_handler()
1354 FLUSH_RX_CHANNEL (dev,rx_channel); in rx_data_av_handler()
1355 clear_bit (rx_busy, &dev->flags); in rx_data_av_handler()
1364 hrz_dev *dev = dev_id; in interrupt_handler() local
1372 while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF) in interrupt_handler()
1393 rx_bus_master_complete_handler (dev); in interrupt_handler()
1398 tx_bus_master_complete_handler (dev); in interrupt_handler()
1403 rx_data_av_handler (dev); in interrupt_handler()
1422 hrz_dev * dev = (hrz_dev *) arg; in do_housekeeping() local
1425 dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF); in do_housekeeping()
1426 dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF); in do_housekeeping()
1427 dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF); in do_housekeeping()
1428 dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF); in do_housekeeping()
1430 mod_timer (&dev->housekeeping, jiffies + HZ/10); in do_housekeeping()
1438 static short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) { in setup_idle_tx_channel() argument
1442 PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev); in setup_idle_tx_channel()
1447 while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) { in setup_idle_tx_channel()
1459 int chan = dev->tx_idle; in setup_idle_tx_channel()
1472 dev->tx_idle = chan; in setup_idle_tx_channel()
1486 spin_lock_irqsave (&dev->mem_lock, flags); in setup_idle_tx_channel()
1489 dev->tx_channel_record[tx_channel] = channel; in setup_idle_tx_channel()
1492 update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS, in setup_idle_tx_channel()
1496 update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS, in setup_idle_tx_channel()
1502 update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS, in setup_idle_tx_channel()
1506 update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS, in setup_idle_tx_channel()
1510 update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS, in setup_idle_tx_channel()
1516 rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK; in setup_idle_tx_channel()
1517 wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK; in setup_idle_tx_channel()
1543 wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC); in setup_idle_tx_channel()
1547 wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr); in setup_idle_tx_channel()
1548 wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr); in setup_idle_tx_channel()
1552 wr_mem (dev, &tx_desc->cell_header, channel); in setup_idle_tx_channel()
1554 spin_unlock_irqrestore (&dev->mem_lock, flags); in setup_idle_tx_channel()
1565 hrz_dev * dev = HRZ_DEV(atm_vcc->dev); in hrz_send() local
1604 pci_read_config_word (dev->pci_dev, PCI_STATUS, &status); in hrz_send()
1608 pci_write_config_word (dev->pci_dev, PCI_STATUS, status); in hrz_send()
1609 if (test_bit (tx_busy, &dev->flags)) { in hrz_send()
1610 hrz_kfree_skb (dev->tx_skb); in hrz_send()
1611 tx_release (dev); in hrz_send()
1632 if (tx_hold (dev)) { in hrz_send()
1646 while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) { in hrz_send()
1656 tx_release (dev); in hrz_send()
1663 if (channel == dev->last_vc) { in hrz_send()
1665 tx_channel = dev->tx_last; in hrz_send()
1670 if (dev->tx_channel_record[tx_channel] == channel) { in hrz_send()
1677 tx_channel = setup_idle_tx_channel (dev, vcc); in hrz_send()
1680 tx_release (dev); in hrz_send()
1686 SELECT_TX_CHANNEL(dev, tx_channel); in hrz_send()
1688 dev->last_vc = channel; in hrz_send()
1689 dev->tx_last = tx_channel; in hrz_send()
1694 YELLOW_LED_OFF(dev); in hrz_send()
1702 dev->tx_skb = skb; in hrz_send()
1706 dev->tx_regions = tx_iovcnt; in hrz_send()
1707 dev->tx_iovec = NULL; /* @@@ needs rewritten */ in hrz_send()
1708 dev->tx_bytes = 0; in hrz_send()
1711 tx_release (dev); in hrz_send()
1716 dev->tx_regions = 0; in hrz_send()
1717 dev->tx_iovec = NULL; in hrz_send()
1718 dev->tx_bytes = tx_len; in hrz_send()
1719 dev->tx_addr = skb->data; in hrz_send()
1725 tx_schedule (dev, 0); in hrz_send()
1734 static void hrz_reset (const hrz_dev * dev) { in hrz_reset() argument
1735 u32 control_0_reg = rd_regl (dev, CONTROL_0_REG); in hrz_reset()
1740 wr_regl (dev, CONTROL_0_REG, control_0_reg); in hrz_reset()
1742 control_0_reg = rd_regl (dev, CONTROL_0_REG); in hrz_reset()
1745 wr_regl (dev, CONTROL_0_REG, control_0_reg | in hrz_reset()
1750 wr_regl (dev, CONTROL_0_REG, control_0_reg); in hrz_reset()
1755 static void WRITE_IT_WAIT (const hrz_dev *dev, u32 ctrl) in WRITE_IT_WAIT() argument
1757 wr_regl (dev, CONTROL_0_REG, ctrl); in WRITE_IT_WAIT()
1761 static void CLOCK_IT (const hrz_dev *dev, u32 ctrl) in CLOCK_IT() argument
1764 WRITE_IT_WAIT(dev, ctrl & ~SEEPROM_SK); in CLOCK_IT()
1765 WRITE_IT_WAIT(dev, ctrl | SEEPROM_SK); in CLOCK_IT()
1768 static u16 read_bia(const hrz_dev *dev, u16 addr) in read_bia() argument
1770 u32 ctrl = rd_regl (dev, CONTROL_0_REG); in read_bia()
1780 WRITE_IT_WAIT(dev, ctrl); in read_bia()
1784 CLOCK_IT(dev, ctrl); in read_bia()
1787 CLOCK_IT(dev, ctrl); in read_bia()
1790 CLOCK_IT(dev, ctrl); in read_bia()
1798 CLOCK_IT(dev, ctrl); in read_bia()
1810 CLOCK_IT(dev, ctrl); in read_bia()
1812 if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO) in read_bia()
1817 WRITE_IT_WAIT(dev, ctrl); in read_bia()
1824 static int hrz_init(hrz_dev *dev) in hrz_init() argument
1839 ctrl = rd_regl (dev, CONTROL_0_REG); in hrz_init()
1852 hrz_reset (dev); in hrz_init()
1859 wr_mem (dev, mem, 0); in hrz_init()
1874 wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf)); in hrz_init()
1875 wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf)); in hrz_init()
1878 wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY); in hrz_init()
1887 wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY); in hrz_init()
1890 wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY); in hrz_init()
1894 wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY); in hrz_init()
1897 wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE); in hrz_init()
1907 wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED); in hrz_init()
1916 wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY); in hrz_init()
1919 wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY); in hrz_init()
1924 wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY); in hrz_init()
1927 wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE); in hrz_init()
1932 wr_regw (dev, TX_CONFIG_OFF, in hrz_init()
1936 wr_regw (dev, RX_CONFIG_OFF, in hrz_init()
1940 wr_regw (dev, RX_LINE_CONFIG_OFF, in hrz_init()
1945 wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF, in hrz_init()
1949 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE); in hrz_init()
1955 wr_regl (dev, CONTROL_0_REG, ctrl); in hrz_init()
1963 wr_regl (dev, CONTROL_0_REG, ctrl); in hrz_init()
1971 if (rd_framer (dev, 0) & 0x00f0) { in hrz_init()
1976 wr_framer (dev, 0x00, 0x0080); in hrz_init()
1977 wr_framer (dev, 0x00, 0x0000); in hrz_init()
1980 wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002); in hrz_init()
1983 wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001); in hrz_init()
1989 wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001); in hrz_init()
1990 wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001); in hrz_init()
1993 wr_framer (dev, 0, 0x0002); in hrz_init()
1996 wr_framer (dev, 2, 0x0B80); in hrz_init()
2008 GREEN_LED_ON(dev); in hrz_init()
2009 YELLOW_LED_ON(dev); in hrz_init()
2016 u8 * esi = dev->atm_dev->esi; in hrz_init()
2026 b = read_bia (dev, i/2 + 2); in hrz_init()
2035 wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS); in hrz_init()
2116 hrz_dev * dev = HRZ_DEV(atm_vcc->dev); in hrz_open() local
2224 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, NULL); in hrz_open()
2232 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0); in hrz_open()
2250 pcr = dev->tx_avail; in hrz_open()
2257 error = make_rate_with_tolerance (dev, pcr, r, 10, in hrz_open()
2290 error = make_rate_with_tolerance (dev, pcr, pr, 10, in hrz_open()
2298 scr = dev->tx_avail; in hrz_open()
2305 error = make_rate_with_tolerance (dev, scr, sr, 10, in hrz_open()
2373 pcr = dev->rx_avail; in hrz_open()
2394 scr = dev->rx_avail; in hrz_open()
2432 spin_lock (&dev->rate_lock); in hrz_open()
2434 if (vcc.tx_rate > dev->tx_avail) { in hrz_open()
2439 if (vcc.rx_rate > dev->rx_avail) { in hrz_open()
2446 dev->tx_avail -= vcc.tx_rate; in hrz_open()
2447 dev->rx_avail -= vcc.rx_rate; in hrz_open()
2453 spin_unlock (&dev->rate_lock); in hrz_open()
2467 if (dev->rxer[channel]) { in hrz_open()
2472 error = hrz_open_rx (dev, channel); in hrz_open()
2478 dev->rxer[channel] = atm_vcc; in hrz_open()
2493 hrz_dev * dev = HRZ_DEV(atm_vcc->dev); in hrz_close() local
2506 while (tx_hold (dev)) in hrz_close()
2510 if (dev->tx_channel_record[i] == channel) { in hrz_close()
2511 dev->tx_channel_record[i] = -1; in hrz_close()
2514 if (dev->last_vc == channel) in hrz_close()
2515 dev->tx_last = -1; in hrz_close()
2516 tx_release (dev); in hrz_close()
2521 hrz_close_rx (dev, channel); in hrz_close()
2523 if (atm_vcc != dev->rxer[channel]) in hrz_close()
2526 atm_vcc, dev->rxer[channel]); in hrz_close()
2527 dev->rxer[channel] = NULL; in hrz_close()
2531 spin_lock (&dev->rate_lock); in hrz_close()
2534 dev->tx_avail += vcc->tx_rate; in hrz_close()
2535 dev->rx_avail += vcc->rx_rate; in hrz_close()
2536 spin_unlock (&dev->rate_lock); in hrz_close()
2547 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2566 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2586 hrz_dev * dev = HRZ_DEV(atm_dev);
2592 hrz_dev * dev = HRZ_DEV(atm_dev);
2599 hrz_dev * dev = HRZ_DEV(atm_dev);
2604 hrz_dev * dev = HRZ_DEV(vcc->dev);
2613 hrz_dev * dev = HRZ_DEV(atm_dev); in hrz_proc_read() local
2625 query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS), in hrz_proc_read()
2626 query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS)); in hrz_proc_read()
2635 dev->tx_cell_count, dev->rx_cell_count, in hrz_proc_read()
2636 dev->hec_error_count, dev->unassigned_cell_count); in hrz_proc_read()
2641 rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF), in hrz_proc_read()
2642 rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF), in hrz_proc_read()
2643 dev->noof_spare_buffers); in hrz_proc_read()
2648 dev->tx_avail, dev->rx_avail); in hrz_proc_read()
2664 hrz_dev * dev; in hrz_probe() local
2684 dev = kzalloc(sizeof(hrz_dev), GFP_KERNEL); in hrz_probe()
2685 if (!dev) { in hrz_probe()
2692 pci_set_drvdata(pci_dev, dev); in hrz_probe()
2700 dev)) { in hrz_probe()
2709 dev->atm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &hrz_ops, -1, in hrz_probe()
2711 if (!(dev->atm_dev)) { in hrz_probe()
2718 dev->atm_dev->number, dev, dev->atm_dev); in hrz_probe()
2719 dev->atm_dev->dev_data = (void *) dev; in hrz_probe()
2720 dev->pci_dev = pci_dev; in hrz_probe()
2737 dev->iobase = iobase; in hrz_probe()
2738 dev->irq = irq; in hrz_probe()
2739 dev->membase = membase; in hrz_probe()
2741 dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0]; in hrz_probe()
2742 dev->rx_q_wrap = &memmap->rx_q_entries[RX_CHANS-1]; in hrz_probe()
2745 dev->last_vc = -1; in hrz_probe()
2746 dev->tx_last = -1; in hrz_probe()
2747 dev->tx_idle = 0; in hrz_probe()
2749 dev->tx_regions = 0; in hrz_probe()
2750 dev->tx_bytes = 0; in hrz_probe()
2751 dev->tx_skb = NULL; in hrz_probe()
2752 dev->tx_iovec = NULL; in hrz_probe()
2754 dev->tx_cell_count = 0; in hrz_probe()
2755 dev->rx_cell_count = 0; in hrz_probe()
2756 dev->hec_error_count = 0; in hrz_probe()
2757 dev->unassigned_cell_count = 0; in hrz_probe()
2759 dev->noof_spare_buffers = 0; in hrz_probe()
2764 dev->tx_channel_record[i] = -1; in hrz_probe()
2767 dev->flags = 0; in hrz_probe()
2774 if (hrz_init(dev)) { in hrz_probe()
2776 dev->tx_avail = ATM_OC3_PCR; in hrz_probe()
2777 dev->rx_avail = ATM_OC3_PCR; in hrz_probe()
2778 set_bit(ultra, &dev->flags); // NOT "|= ultra" ! in hrz_probe()
2780 dev->tx_avail = ((25600000/8)*26)/(27*53); in hrz_probe()
2781 dev->rx_avail = ((25600000/8)*26)/(27*53); in hrz_probe()
2786 spin_lock_init(&dev->rate_lock); in hrz_probe()
2790 spin_lock_init(&dev->mem_lock); in hrz_probe()
2792 init_waitqueue_head(&dev->tx_queue); in hrz_probe()
2795 dev->atm_dev->ci_range.vpi_bits = vpi_bits; in hrz_probe()
2796 dev->atm_dev->ci_range.vci_bits = 10-vpi_bits; in hrz_probe()
2798 init_timer(&dev->housekeeping); in hrz_probe()
2799 dev->housekeeping.function = do_housekeeping; in hrz_probe()
2800 dev->housekeeping.data = (unsigned long) dev; in hrz_probe()
2801 mod_timer(&dev->housekeeping, jiffies); in hrz_probe()
2807 free_irq(dev->irq, dev); in hrz_probe()
2809 kfree(dev); in hrz_probe()
2819 hrz_dev *dev; in hrz_remove_one() local
2821 dev = pci_get_drvdata(pci_dev); in hrz_remove_one()
2823 PRINTD(DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev); in hrz_remove_one()
2824 del_timer_sync(&dev->housekeeping); in hrz_remove_one()
2825 hrz_reset(dev); in hrz_remove_one()
2826 atm_dev_deregister(dev->atm_dev); in hrz_remove_one()
2827 free_irq(dev->irq, dev); in hrz_remove_one()
2828 release_region(dev->iobase, HRZ_IO_EXTENT); in hrz_remove_one()
2829 kfree(dev); in hrz_remove_one()