Lines Matching refs:u32
90 u32 clp : 1, /* cell loss priority */
91 u32 plt : 3, /* payload type */
92 u32 vci : 16, /* virtual channel identifier */
93 u32 vpi : 8, /* virtual path identifier */
94 u32 gfc : 4 /* generic flow control */
112 u32 length : 16, /* total PDU length */
113 u32 nseg : 8, /* number of transmit segments */
115 u32 intr : 4 /* interrupt requested */
125 u32 idle_cells : 16, /* number of idle cells to insert */
126 u32 data_cells : 16 /* number of data cells to transmit */
134 u32 buffer; /* transmit buffer DMA address */
135 u32 length; /* number of bytes in buffer */
145 u32 pad; /* reserved */
153 u32 handle; /* host supplied receive buffer handle */
154 u32 length; /* number of bytes in buffer */
162 u32 nseg; /* number of receive segments */
188 u32 handle; /* host supplied handle */
189 u32 buffer_haddr; /* host DMA address of host buffer */
204 u32 size : 4, /* tpd size expressed in 32 byte blocks */
205 u32 pad : 1, /* reserved */
206 u32 haddr : 27 /* tpd DMA addr aligned on 32 byte boundary */
216 u32 status_haddr; /* host DMA address of completion status */
223 u32 rpd_haddr; /* host DMA address of rpd */
224 u32 status_haddr; /* host DMA address of completion status */
231 u32 rbd_block_haddr; /* host DMA address of rbd block */
232 u32 status_haddr; /* host DMA address of completion status */
270 u32 vci : 16, /* virtual channel identifier */
271 u32 vpi : 8, /* virtual path identifier */
272 u32 pad : 8 /* reserved */
284 u32 pad : 8 /* reserved */
294 u32 mtu; /* for AAL0 only */
304 u32 pad : 24 /* reserved */
320 u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite
331 u32 reg : 8, /* register index */
332 u32 value : 8, /* register value */
333 u32 mask : 8 /* register mask that specifies which
344 u32 regs_haddr; /* host DMA address of OC-3 regs buffer */
456 u32 pad : 24 /* reserved */
465 u32 stats_haddr; /* host DMA address of stats buffer */
472 u32 hw_revision; /* hardware revision */
473 u32 serial_number; /* board serial number */
483 u32 pad : 24 /* reserved */
492 u32 prom_haddr; /* host DMA address of PROM buffer */
505 u32 pad[ 4 ]; /* i960 padding */
513 u32 status_haddr; /* host DMA address of completion status */
514 u32 pad[ 3 ]; /* i960 padding */
524 u32 tpd_dma; /* DMA address of tpd */
539 u32 rpd_dma; /* DMA address of rpd */
549 u32 rbd_block_dma; /* DMA address od rdb */
568 u32 alloc_size; /* length of allocated chunk */
569 u32 align_size; /* length of aligned chunk */
590 #define FORE200E_BUF2HDL(buffer) ((u32)(buffer))
593 #define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer)))
657 u32 queue_length; /* queue capacity */
658 u32 buffer_size; /* host buffer size */
659 u32 pool_size; /* number of rbds */
660 u32 supply_blksize; /* num of rbds in I/O block (multiple
670 u32 receive_threshold; /* not used */
671 u32 num_connect; /* ATM connections */
672 u32 cmd_queue_len; /* length of command queue */
673 u32 tx_queue_len; /* length of transmit queue */
674 u32 rx_queue_len; /* length of receive queue */
675 u32 rsd_extension; /* number of extra 32 byte blocks */
676 u32 tsd_extension; /* number of extra 32 byte blocks */
677 u32 conless_vpvc; /* not used */
678 u32 pad[ 2 ]; /* force quad alignment */
697 u32 cp_cmdq; /* command queue */
698 u32 cp_txq; /* transmit queue */
699 u32 cp_rxq; /* receive queue */
700 …u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues */
701 u32 imask; /* 1 enables cp to host interrupts */
702 u32 istat; /* 1 for interrupt posted */
703 u32 heap_base; /* offset form beginning of ram */
704 u32 heap_size; /* space available for queues */
705 u32 hlogger; /* non zero for host logging */
706 u32 heartbeat; /* cp heartbeat */
707 u32 fw_release; /* firmware version */
708 u32 mon960_release; /* i960 monitor version */
709 u32 tq_plen; /* transmit throughput measurements */
713 u32 oc3_revision; /* OC-3 revision number */
720 BSTAT_COLD_START = (u32) 0xc01dc01d, /* cold start */
721 BSTAT_SELFTEST_OK = (u32) 0x02201958, /* self-test ok */
722 BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad, /* self-test failed */
723 BSTAT_CP_RUNNING = (u32) 0xce11feed, /* cp is running */
724 BSTAT_MON_TOO_BIG = (u32) 0x10aded00 /* i960 monitor is too big */
731 u32 send; /* write register */
732 u32 recv; /* read register */
744 u32 app_base; /* application base offset */
745 u32 mon_version; /* i960 monitor version */
772 volatile u32 __iomem * hcr; /* address of host control register */
773 volatile u32 __iomem * imr; /* address of host interrupt mask register */
774 volatile u32 __iomem * psr; /* address of PCI specific register */
781 u32 __iomem *hcr; /* address of host control register */
782 u32 __iomem *bsr; /* address of burst transfer size register */
783 u32 __iomem *isr; /* address of interrupt level selection register */
805 u32 (*read)(volatile u32 __iomem *);
806 void (*write)(u32, volatile u32 __iomem *);
807 u32 (*dma_map)(struct fore200e*, void*, int, int);
808 void (*dma_unmap)(struct fore200e*, u32, int, int);
809 void (*dma_sync_for_cpu)(struct fore200e*, u32, int, int);
810 void (*dma_sync_for_device)(struct fore200e*, u32, int, int);
861 u32 available_cell_rate; /* remaining pseudo-CBR bw on link */