509 	readl(dimm_mmio);	/* MMIO PCI posting flush */  in pdc20621_dma_prep()
544 	readl(dimm_mmio);	/* MMIO PCI posting flush */  in pdc20621_nodata_prep()
575 	readl(mmio + PDC_20621_SEQCTL + (seq * 4));	/* flush */  in __pdc20621_push_hdma()
578 	readl(mmio + PDC_HDMA_PKT_SUBMIT);	/* flush */  in __pdc20621_push_hdma()
628 	printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));  in pdc20621_dump_hdma()
629 	printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));  in pdc20621_dump_hdma()
630 	printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));  in pdc20621_dump_hdma()
631 	printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));  in pdc20621_dump_hdma()
668 		readl(mmio + PDC_20621_SEQCTL + (seq * 4));	/* flush */  in pdc20621_packet_start()
672 		readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);  in pdc20621_packet_start()
721 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
732 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
747 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
751 			readl(mmio + PDC_20621_SEQCTL + (seq * 4));  in pdc20621_host_intr()
754 			readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);  in pdc20621_host_intr()
760 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
809 	mask = readl(mmio_base + PDC_20621_SEQMASK);  in pdc20621_interrupt()
860 	tmp = readl(mmio + PDC_CTLSTAT);  in pdc_freeze()
864 	readl(mmio + PDC_CTLSTAT); /* flush */  in pdc_freeze()
878 	tmp = readl(mmio + PDC_CTLSTAT);  in pdc_thaw()
881 	readl(mmio + PDC_CTLSTAT); /* flush */  in pdc_thaw()
893 		tmp = readl(mmio);  in pdc_reset_port()
905 	readl(mmio);	/* flush */  in pdc_reset_port()
1015 	readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1017 	readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1029 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1031 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1040 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1042 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1067 	readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1074 	readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1080 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1083 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1091 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1094 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1115 	readl(mmio + PDC_I2C_ADDR_DATA);  in pdc20621_i2c_read()
1122 		status = readl(mmio + PDC_I2C_CONTROL);  in pdc20621_i2c_read()
1124 			status = readl(mmio + PDC_I2C_ADDR_DATA);  in pdc20621_i2c_read()
1215 	readl(mmio + PDC_DIMM0_CONTROL);  in pdc20621_prog_dimm0()
1238 	readl(mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1250 		readl(mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1261 		data = readl(mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1290 	time_period = readl(mmio + PDC_TIME_PERIOD);  in pdc20621_dimm_init()
1295 	readl(mmio + PDC_TIME_CONTROL);  in pdc20621_dimm_init()
1305 	tcount = readl(mmio + PDC_TIME_COUNTER);  in pdc20621_dimm_init()
1334 	readl(mmio + PDC_CTL_STATUS);  in pdc20621_dimm_init()
1422 	tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;  in pdc_20621_init()
1429 	tmp = readl(mmio + PDC_HDMA_CTLSTAT);  in pdc_20621_init()
1432 	readl(mmio + PDC_HDMA_CTLSTAT);		/* flush */  in pdc_20621_init()
1436 	tmp = readl(mmio + PDC_HDMA_CTLSTAT);  in pdc_20621_init()
1439 	readl(mmio + PDC_HDMA_CTLSTAT);		/* flush */  in pdc_20621_init()