118 	NV_ADMA_CTL			= 0x40,  enumerator
625 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_register_mode()
626 	writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);  in nv_adma_register_mode()
655 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_mode()
656 	writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);  in nv_adma_mode()
1056 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_freeze()
1058 		mmio + NV_ADMA_CTL);  in nv_adma_freeze()
1059 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_freeze()
1074 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_thaw()
1076 		mmio + NV_ADMA_CTL);  in nv_adma_thaw()
1077 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_thaw()
1206 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1208 		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1210 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1211 	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1212 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_start()
1214 	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1215 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_start()
1226 	writew(0, mmio + NV_ADMA_CTL);  in nv_adma_port_stop()
1242 	writew(0, mmio + NV_ADMA_CTL);  in nv_adma_port_suspend()
1267 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1269 		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1271 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1272 	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1273 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_resume()
1275 	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1276 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_resume()
1715 		tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1716 		writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1717 		readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_error_handler()
1719 		writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1720 		readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_error_handler()