104 static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)  in xgene_ahci_init_memram()  argument
106 	dev_dbg(ctx->dev, "Release memory from shutdown\n");  in xgene_ahci_init_memram()
107 	writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);  in xgene_ahci_init_memram()
108 	readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */  in xgene_ahci_init_memram()
110 	if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {  in xgene_ahci_init_memram()
111 		dev_err(ctx->dev, "failed to release memory from shutdown\n");  in xgene_ahci_init_memram()
206 	struct xgene_ahci_context *ctx = hpriv->plat_data;  in xgene_ahci_qc_issue()  local
215 	if (ctx->class[ap->port_no] == ATA_DEV_PMP) {  in xgene_ahci_qc_issue()
222 	if (unlikely((ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA) ||  in xgene_ahci_qc_issue()
223 	    (ctx->last_cmd[ap->port_no] == ATA_CMD_PACKET) ||  in xgene_ahci_qc_issue()
224 	    (ctx->last_cmd[ap->port_no] == ATA_CMD_SMART)))  in xgene_ahci_qc_issue()
230 	ctx->last_cmd[ap->port_no] = qc->tf.command;  in xgene_ahci_qc_issue()
235 static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)  in xgene_ahci_is_memram_inited()  argument
237 	void __iomem *diagcsr = ctx->csr_diag;  in xgene_ahci_is_memram_inited()
280 static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)  in xgene_ahci_set_phy_cfg()  argument
282 	void __iomem *mmio = ctx->hpriv->mmio;  in xgene_ahci_set_phy_cfg()
285 	dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",  in xgene_ahci_set_phy_cfg()
369 	struct xgene_ahci_context *ctx = hpriv->plat_data;  in xgene_ahci_do_hardreset()  local
388 				dev_warn(ctx->dev, "link has error\n");  in xgene_ahci_do_hardreset()
514 	struct xgene_ahci_context *ctx = hpriv->plat_data;  in xgene_ahci_softreset()  local
536 	ctx->class[ap->port_no] = *class;  in xgene_ahci_softreset()
584 	struct xgene_ahci_context *ctx = hpriv->plat_data;  in xgene_ahci_hw_init()  local
590 	rc = xgene_ahci_init_memram(ctx);  in xgene_ahci_hw_init()
595 		xgene_ahci_set_phy_cfg(ctx, i);  in xgene_ahci_hw_init()
600 	writel(0, ctx->csr_core + INTSTATUSMASK);  in xgene_ahci_hw_init()
601 	val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */  in xgene_ahci_hw_init()
602 	dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",  in xgene_ahci_hw_init()
605 	writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);  in xgene_ahci_hw_init()
606 	readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */  in xgene_ahci_hw_init()
607 	writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);  in xgene_ahci_hw_init()
608 	readl(ctx->csr_axi + INT_SLV_TMOMASK);  in xgene_ahci_hw_init()
611 	writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);  in xgene_ahci_hw_init()
612 	writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);  in xgene_ahci_hw_init()
613 	writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);  in xgene_ahci_hw_init()
614 	writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);  in xgene_ahci_hw_init()
617 	val = readl(ctx->csr_core + BUSCTLREG);  in xgene_ahci_hw_init()
620 	writel(val, ctx->csr_core + BUSCTLREG);  in xgene_ahci_hw_init()
622 	val = readl(ctx->csr_core + IOFMSTRWAUX);  in xgene_ahci_hw_init()
625 	writel(val, ctx->csr_core + IOFMSTRWAUX);  in xgene_ahci_hw_init()
626 	val = readl(ctx->csr_core + IOFMSTRWAUX);  in xgene_ahci_hw_init()
627 	dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",  in xgene_ahci_hw_init()
633 static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)  in xgene_ahci_mux_select()  argument
638 	if (!ctx->csr_mux)  in xgene_ahci_mux_select()
641 	val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);  in xgene_ahci_mux_select()
643 	writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);  in xgene_ahci_mux_select()
644 	val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);  in xgene_ahci_mux_select()
672 	struct xgene_ahci_context *ctx;  in xgene_ahci_probe()  local
684 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);  in xgene_ahci_probe()
685 	if (!ctx)  in xgene_ahci_probe()
688 	hpriv->plat_data = ctx;  in xgene_ahci_probe()
689 	ctx->hpriv = hpriv;  in xgene_ahci_probe()
690 	ctx->dev = dev;  in xgene_ahci_probe()
694 	ctx->csr_core = devm_ioremap_resource(dev, res);  in xgene_ahci_probe()
695 	if (IS_ERR(ctx->csr_core))  in xgene_ahci_probe()
696 		return PTR_ERR(ctx->csr_core);  in xgene_ahci_probe()
700 	ctx->csr_diag = devm_ioremap_resource(dev, res);  in xgene_ahci_probe()
701 	if (IS_ERR(ctx->csr_diag))  in xgene_ahci_probe()
702 		return PTR_ERR(ctx->csr_diag);  in xgene_ahci_probe()
706 	ctx->csr_axi = devm_ioremap_resource(dev, res);  in xgene_ahci_probe()
707 	if (IS_ERR(ctx->csr_axi))  in xgene_ahci_probe()
708 		return PTR_ERR(ctx->csr_axi);  in xgene_ahci_probe()
717 		ctx->csr_mux = csr;  in xgene_ahci_probe()
749 	dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,  in xgene_ahci_probe()
753 	if ((rc = xgene_ahci_mux_select(ctx))) {  in xgene_ahci_probe()
758 	if (xgene_ahci_is_memram_inited(ctx)) {  in xgene_ahci_probe()