115 	struct tegra_ahci_priv *tegra = hpriv->plat_data;  in tegra_ahci_power_on()  local
118 	ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),  in tegra_ahci_power_on()
119 				    tegra->supplies);  in tegra_ahci_power_on()
124 						tegra->sata_clk,  in tegra_ahci_power_on()
125 						tegra->sata_rst);  in tegra_ahci_power_on()
129 	reset_control_assert(tegra->sata_oob_rst);  in tegra_ahci_power_on()
130 	reset_control_assert(tegra->sata_cold_rst);  in tegra_ahci_power_on()
136 	reset_control_deassert(tegra->sata_cold_rst);  in tegra_ahci_power_on()
137 	reset_control_deassert(tegra->sata_oob_rst);  in tegra_ahci_power_on()
142 	clk_disable_unprepare(tegra->sata_clk);  in tegra_ahci_power_on()
147 	regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);  in tegra_ahci_power_on()
154 	struct tegra_ahci_priv *tegra = hpriv->plat_data;  in tegra_ahci_power_off()  local
158 	reset_control_assert(tegra->sata_rst);  in tegra_ahci_power_off()
159 	reset_control_assert(tegra->sata_oob_rst);  in tegra_ahci_power_off()
160 	reset_control_assert(tegra->sata_cold_rst);  in tegra_ahci_power_off()
162 	clk_disable_unprepare(tegra->sata_clk);  in tegra_ahci_power_off()
165 	regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);  in tegra_ahci_power_off()
170 	struct tegra_ahci_priv *tegra = hpriv->plat_data;  in tegra_ahci_controller_init()  local
177 		dev_err(&tegra->pdev->dev,  in tegra_ahci_controller_init()
182 	val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);  in tegra_ahci_controller_init()
184 	writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);  in tegra_ahci_controller_init()
190 		dev_err(&tegra->pdev->dev,  in tegra_ahci_controller_init()
197 	writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);  in tegra_ahci_controller_init()
199 	val = readl(tegra->sata_regs +  in tegra_ahci_controller_init()
207 	writel(val, tegra->sata_regs + SCFG_OFFSET +  in tegra_ahci_controller_init()
210 	val = readl(tegra->sata_regs +  in tegra_ahci_controller_init()
218 	writel(val, tegra->sata_regs + SCFG_OFFSET +  in tegra_ahci_controller_init()
222 		tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);  in tegra_ahci_controller_init()
224 		tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);  in tegra_ahci_controller_init()
226 	writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);  in tegra_ahci_controller_init()
230 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
232 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
234 	writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);  in tegra_ahci_controller_init()
236 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
238 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
242 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);  in tegra_ahci_controller_init()
245 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);  in tegra_ahci_controller_init()
250 	       tegra->sata_regs + SATA_FPCI_BAR5);  in tegra_ahci_controller_init()
253 	       tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);  in tegra_ahci_controller_init()
257 	val = readl(tegra->sata_regs + SATA_INTR_MASK);  in tegra_ahci_controller_init()
259 	writel(val, tegra->sata_regs + SATA_INTR_MASK);  in tegra_ahci_controller_init()
301 	struct tegra_ahci_priv *tegra;  in tegra_ahci_probe()  local
309 	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);  in tegra_ahci_probe()
310 	if (!tegra)  in tegra_ahci_probe()
313 	hpriv->plat_data = tegra;  in tegra_ahci_probe()
315 	tegra->pdev = pdev;  in tegra_ahci_probe()
318 	tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);  in tegra_ahci_probe()
319 	if (IS_ERR(tegra->sata_regs))  in tegra_ahci_probe()
320 		return PTR_ERR(tegra->sata_regs);  in tegra_ahci_probe()
322 	tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");  in tegra_ahci_probe()
323 	if (IS_ERR(tegra->sata_rst)) {  in tegra_ahci_probe()
325 		return PTR_ERR(tegra->sata_rst);  in tegra_ahci_probe()
328 	tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");  in tegra_ahci_probe()
329 	if (IS_ERR(tegra->sata_oob_rst)) {  in tegra_ahci_probe()
331 		return PTR_ERR(tegra->sata_oob_rst);  in tegra_ahci_probe()
334 	tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");  in tegra_ahci_probe()
335 	if (IS_ERR(tegra->sata_cold_rst)) {  in tegra_ahci_probe()
337 		return PTR_ERR(tegra->sata_cold_rst);  in tegra_ahci_probe()
340 	tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");  in tegra_ahci_probe()
341 	if (IS_ERR(tegra->sata_clk)) {  in tegra_ahci_probe()
343 		return PTR_ERR(tegra->sata_clk);  in tegra_ahci_probe()
346 	tegra->supplies[0].supply = "avdd";  in tegra_ahci_probe()
347 	tegra->supplies[1].supply = "hvdd";  in tegra_ahci_probe()
348 	tegra->supplies[2].supply = "vddio";  in tegra_ahci_probe()
349 	tegra->supplies[3].supply = "target-5v";  in tegra_ahci_probe()
350 	tegra->supplies[4].supply = "target-12v";  in tegra_ahci_probe()
352 	ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),  in tegra_ahci_probe()
353 				      tegra->supplies);  in tegra_ahci_probe()