Lines Matching refs:C
74 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
76 static const u32 xtensa_cache_ctl[][C(OP_MAX)][C(RESULT_MAX)] = {
77 [C(L1D)] = {
78 [C(OP_READ)] = {
79 [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(10, 0x1),
80 [C(RESULT_MISS)] = XTENSA_PMU_MASK(10, 0x2),
82 [C(OP_WRITE)] = {
83 [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(11, 0x1),
84 [C(RESULT_MISS)] = XTENSA_PMU_MASK(11, 0x2),
87 [C(L1I)] = {
88 [C(OP_READ)] = {
89 [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(8, 0x1),
90 [C(RESULT_MISS)] = XTENSA_PMU_MASK(8, 0x2),
93 [C(DTLB)] = {
94 [C(OP_READ)] = {
95 [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(9, 0x1),
96 [C(RESULT_MISS)] = XTENSA_PMU_MASK(9, 0x8),
99 [C(ITLB)] = {
100 [C(OP_READ)] = {
101 [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(7, 0x1),
102 [C(RESULT_MISS)] = XTENSA_PMU_MASK(7, 0x8),
117 cache_op >= C(OP_MAX) || in xtensa_pmu_cache_event()
118 cache_result >= C(RESULT_MAX)) in xtensa_pmu_cache_event()