124 static inline bool is_amd_pmu_msr(unsigned int msr)  in is_amd_pmu_msr()  argument
126 	if ((msr >= MSR_F15H_PERF_CTL &&  in is_amd_pmu_msr()
127 	     msr < MSR_F15H_PERF_CTR + (amd_num_counters * 2)) ||  in is_amd_pmu_msr()
128 	    (msr >= MSR_K7_EVNTSEL0 &&  in is_amd_pmu_msr()
129 	     msr < MSR_K7_PERFCTR0 + amd_num_counters))  in is_amd_pmu_msr()
181 static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,  in xen_intel_pmu_emulate()  argument
197 	switch (msr) {  in xen_intel_pmu_emulate()
235 			if (msr == MSR_CORE_PERF_GLOBAL_OVF_CTRL)  in xen_intel_pmu_emulate()
244 static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)  in xen_amd_pmu_emulate()  argument
257 	    ((msr >= MSR_K7_EVNTSEL0) && (msr <= MSR_K7_PERFCTR3)))  in xen_amd_pmu_emulate()
258 		msr = get_fam15h_addr(msr);  in xen_amd_pmu_emulate()
262 		if (msr == amd_ctrls_base + off) {  in xen_amd_pmu_emulate()
266 		} else if (msr == amd_counters_base + off) {  in xen_amd_pmu_emulate()
285 bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)  in pmu_msr_read()  argument
288 		if (is_amd_pmu_msr(msr)) {  in pmu_msr_read()
289 			if (!xen_amd_pmu_emulate(msr, val, 1))  in pmu_msr_read()
290 				*val = native_read_msr_safe(msr, err);  in pmu_msr_read()
296 		if (is_intel_pmu_msr(msr, &type, &index)) {  in pmu_msr_read()
297 			if (!xen_intel_pmu_emulate(msr, val, type, index, 1))  in pmu_msr_read()
298 				*val = native_read_msr_safe(msr, err);  in pmu_msr_read()
306 bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err)  in pmu_msr_write()  argument
311 		if (is_amd_pmu_msr(msr)) {  in pmu_msr_write()
312 			if (!xen_amd_pmu_emulate(msr, &val, 0))  in pmu_msr_write()
313 				*err = native_write_msr_safe(msr, low, high);  in pmu_msr_write()
319 		if (is_intel_pmu_msr(msr, &type, &index)) {  in pmu_msr_write()
320 			if (!xen_intel_pmu_emulate(msr, &val, type, index, 0))  in pmu_msr_write()
321 				*err = native_write_msr_safe(msr, low, high);  in pmu_msr_write()
337 		uint32_t msr;  in xen_amd_read_pmc()  local
340 		msr = amd_counters_base + (counter * amd_msr_step);  in xen_amd_read_pmc()
341 		return native_read_msr_safe(msr, &err);  in xen_amd_read_pmc()
358 		uint32_t msr;  in xen_intel_read_pmc()  local
362 			msr = MSR_CORE_PERF_FIXED_CTR0 + (counter & 0xffff);  in xen_intel_read_pmc()
364 			msr = MSR_IA32_PERFCTR0 + counter;  in xen_intel_read_pmc()
366 		return native_read_msr_safe(msr, &err);  in xen_intel_read_pmc()