273 	int i;  in op_mux_switch_ctrl()  local
276 	for (i = 0; i < num_counters; ++i) {  in op_mux_switch_ctrl()
277 		int virt = op_x86_phys_to_virt(i);  in op_mux_switch_ctrl()
280 		rdmsrl(msrs->controls[i].addr, val);  in op_mux_switch_ctrl()
283 		wrmsrl(msrs->controls[i].addr, val);  in op_mux_switch_ctrl()
293 	int i;  in op_amd_shutdown()  local
295 	for (i = 0; i < num_counters; ++i) {  in op_amd_shutdown()
296 		if (!msrs->counters[i].addr)  in op_amd_shutdown()
298 		release_perfctr_nmi(MSR_K7_PERFCTR0 + i);  in op_amd_shutdown()
299 		release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);  in op_amd_shutdown()
305 	int i;  in op_amd_fill_in_addresses()  local
307 	for (i = 0; i < num_counters; i++) {  in op_amd_fill_in_addresses()
308 		if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))  in op_amd_fill_in_addresses()
310 		if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {  in op_amd_fill_in_addresses()
311 			release_perfctr_nmi(MSR_K7_PERFCTR0 + i);  in op_amd_fill_in_addresses()
316 			msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1);  in op_amd_fill_in_addresses()
317 			msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);  in op_amd_fill_in_addresses()
319 			msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;  in op_amd_fill_in_addresses()
320 			msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;  in op_amd_fill_in_addresses()
324 		if (!counter_config[i].enabled)  in op_amd_fill_in_addresses()
326 		op_x86_warn_reserved(i);  in op_amd_fill_in_addresses()
338 	int i;  in op_amd_setup_ctrs()  local
341 	for (i = 0; i < OP_MAX_COUNTER; ++i) {  in op_amd_setup_ctrs()
342 		if (counter_config[i].enabled  in op_amd_setup_ctrs()
343 		    && msrs->counters[op_x86_virt_to_phys(i)].addr)  in op_amd_setup_ctrs()
344 			reset_value[i] = counter_config[i].count;  in op_amd_setup_ctrs()
346 			reset_value[i] = 0;  in op_amd_setup_ctrs()
350 	for (i = 0; i < num_counters; ++i) {  in op_amd_setup_ctrs()
351 		if (!msrs->controls[i].addr)  in op_amd_setup_ctrs()
353 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
355 			op_x86_warn_in_use(i);  in op_amd_setup_ctrs()
357 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
362 		wrmsrl(msrs->counters[i].addr, -1LL);  in op_amd_setup_ctrs()
366 	for (i = 0; i < num_counters; ++i) {  in op_amd_setup_ctrs()
367 		int virt = op_x86_phys_to_virt(i);  in op_amd_setup_ctrs()
372 		wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);  in op_amd_setup_ctrs()
375 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
378 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
386 	int i;  in op_amd_check_ctrs()  local
388 	for (i = 0; i < num_counters; ++i) {  in op_amd_check_ctrs()
389 		int virt = op_x86_phys_to_virt(i);  in op_amd_check_ctrs()
392 		rdmsrl(msrs->counters[i].addr, val);  in op_amd_check_ctrs()
397 		wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);  in op_amd_check_ctrs()
409 	int i;  in op_amd_start()  local
411 	for (i = 0; i < num_counters; ++i) {  in op_amd_start()
412 		if (!reset_value[op_x86_phys_to_virt(i)])  in op_amd_start()
414 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_start()
416 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_start()
425 	int i;  in op_amd_stop()  local
431 	for (i = 0; i < num_counters; ++i) {  in op_amd_stop()
432 		if (!reset_value[op_x86_phys_to_virt(i)])  in op_amd_stop()
434 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_stop()
436 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_stop()