Lines Matching refs:C
316 [ C(L1D ) ] = {
317 [ C(OP_READ) ] = {
318 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
319 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
321 [ C(OP_WRITE) ] = {
322 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
323 [ C(RESULT_MISS) ] = 0x0,
325 [ C(OP_PREFETCH) ] = {
326 [ C(RESULT_ACCESS) ] = 0x0,
327 [ C(RESULT_MISS) ] = 0x0,
330 [ C(L1I ) ] = {
331 [ C(OP_READ) ] = {
332 [ C(RESULT_ACCESS) ] = 0x0,
333 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
335 [ C(OP_WRITE) ] = {
336 [ C(RESULT_ACCESS) ] = -1,
337 [ C(RESULT_MISS) ] = -1,
339 [ C(OP_PREFETCH) ] = {
340 [ C(RESULT_ACCESS) ] = 0x0,
341 [ C(RESULT_MISS) ] = 0x0,
344 [ C(LL ) ] = {
345 [ C(OP_READ) ] = {
346 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
347 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
349 [ C(OP_WRITE) ] = {
350 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
351 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
353 [ C(OP_PREFETCH) ] = {
354 [ C(RESULT_ACCESS) ] = 0x0,
355 [ C(RESULT_MISS) ] = 0x0,
358 [ C(DTLB) ] = {
359 [ C(OP_READ) ] = {
360 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
361 [ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
363 [ C(OP_WRITE) ] = {
364 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
365 [ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */
367 [ C(OP_PREFETCH) ] = {
368 [ C(RESULT_ACCESS) ] = 0x0,
369 [ C(RESULT_MISS) ] = 0x0,
372 [ C(ITLB) ] = {
373 [ C(OP_READ) ] = {
374 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
375 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
377 [ C(OP_WRITE) ] = {
378 [ C(RESULT_ACCESS) ] = -1,
379 [ C(RESULT_MISS) ] = -1,
381 [ C(OP_PREFETCH) ] = {
382 [ C(RESULT_ACCESS) ] = -1,
383 [ C(RESULT_MISS) ] = -1,
386 [ C(BPU ) ] = {
387 [ C(OP_READ) ] = {
388 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
389 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
391 [ C(OP_WRITE) ] = {
392 [ C(RESULT_ACCESS) ] = -1,
393 [ C(RESULT_MISS) ] = -1,
395 [ C(OP_PREFETCH) ] = {
396 [ C(RESULT_ACCESS) ] = -1,
397 [ C(RESULT_MISS) ] = -1,
400 [ C(NODE) ] = {
401 [ C(OP_READ) ] = {
402 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
403 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
405 [ C(OP_WRITE) ] = {
406 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
407 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
409 [ C(OP_PREFETCH) ] = {
410 [ C(RESULT_ACCESS) ] = 0x0,
411 [ C(RESULT_MISS) ] = 0x0,
421 [ C(LL ) ] = {
422 [ C(OP_READ) ] = {
423 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
425 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
429 [ C(OP_WRITE) ] = {
430 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
432 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
436 [ C(OP_PREFETCH) ] = {
437 [ C(RESULT_ACCESS) ] = 0x0,
438 [ C(RESULT_MISS) ] = 0x0,
441 [ C(NODE) ] = {
442 [ C(OP_READ) ] = {
443 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
445 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
448 [ C(OP_WRITE) ] = {
449 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
451 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
454 [ C(OP_PREFETCH) ] = {
455 [ C(RESULT_ACCESS) ] = 0x0,
456 [ C(RESULT_MISS) ] = 0x0,
509 [ C(LL ) ] = {
510 [ C(OP_READ) ] = {
511 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
512 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
514 [ C(OP_WRITE) ] = {
515 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
516 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
518 [ C(OP_PREFETCH) ] = {
519 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
520 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
523 [ C(NODE) ] = {
524 [ C(OP_READ) ] = {
525 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
526 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
528 [ C(OP_WRITE) ] = {
529 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
530 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
532 [ C(OP_PREFETCH) ] = {
533 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
534 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
544 [ C(L1D) ] = {
545 [ C(OP_READ) ] = {
546 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
547 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
549 [ C(OP_WRITE) ] = {
550 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
551 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
553 [ C(OP_PREFETCH) ] = {
554 [ C(RESULT_ACCESS) ] = 0x0,
555 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
558 [ C(L1I ) ] = {
559 [ C(OP_READ) ] = {
560 [ C(RESULT_ACCESS) ] = 0x0,
561 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
563 [ C(OP_WRITE) ] = {
564 [ C(RESULT_ACCESS) ] = -1,
565 [ C(RESULT_MISS) ] = -1,
567 [ C(OP_PREFETCH) ] = {
568 [ C(RESULT_ACCESS) ] = 0x0,
569 [ C(RESULT_MISS) ] = 0x0,
572 [ C(LL ) ] = {
573 [ C(OP_READ) ] = {
575 [ C(RESULT_ACCESS) ] = 0x01b7,
577 [ C(RESULT_MISS) ] = 0x01b7,
579 [ C(OP_WRITE) ] = {
581 [ C(RESULT_ACCESS) ] = 0x01b7,
583 [ C(RESULT_MISS) ] = 0x01b7,
585 [ C(OP_PREFETCH) ] = {
587 [ C(RESULT_ACCESS) ] = 0x01b7,
589 [ C(RESULT_MISS) ] = 0x01b7,
592 [ C(DTLB) ] = {
593 [ C(OP_READ) ] = {
594 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
595 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
597 [ C(OP_WRITE) ] = {
598 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
599 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
601 [ C(OP_PREFETCH) ] = {
602 [ C(RESULT_ACCESS) ] = 0x0,
603 [ C(RESULT_MISS) ] = 0x0,
606 [ C(ITLB) ] = {
607 [ C(OP_READ) ] = {
608 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
609 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
611 [ C(OP_WRITE) ] = {
612 [ C(RESULT_ACCESS) ] = -1,
613 [ C(RESULT_MISS) ] = -1,
615 [ C(OP_PREFETCH) ] = {
616 [ C(RESULT_ACCESS) ] = -1,
617 [ C(RESULT_MISS) ] = -1,
620 [ C(BPU ) ] = {
621 [ C(OP_READ) ] = {
622 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
623 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
625 [ C(OP_WRITE) ] = {
626 [ C(RESULT_ACCESS) ] = -1,
627 [ C(RESULT_MISS) ] = -1,
629 [ C(OP_PREFETCH) ] = {
630 [ C(RESULT_ACCESS) ] = -1,
631 [ C(RESULT_MISS) ] = -1,
634 [ C(NODE) ] = {
635 [ C(OP_READ) ] = {
636 [ C(RESULT_ACCESS) ] = 0x01b7,
637 [ C(RESULT_MISS) ] = 0x01b7,
639 [ C(OP_WRITE) ] = {
640 [ C(RESULT_ACCESS) ] = 0x01b7,
641 [ C(RESULT_MISS) ] = 0x01b7,
643 [ C(OP_PREFETCH) ] = {
644 [ C(RESULT_ACCESS) ] = 0x01b7,
645 [ C(RESULT_MISS) ] = 0x01b7,
700 [ C(L1D ) ] = {
701 [ C(OP_READ) ] = {
702 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
703 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
705 [ C(OP_WRITE) ] = {
706 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
707 [ C(RESULT_MISS) ] = 0x0,
709 [ C(OP_PREFETCH) ] = {
710 [ C(RESULT_ACCESS) ] = 0x0,
711 [ C(RESULT_MISS) ] = 0x0,
714 [ C(L1I ) ] = {
715 [ C(OP_READ) ] = {
716 [ C(RESULT_ACCESS) ] = 0x0,
717 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
719 [ C(OP_WRITE) ] = {
720 [ C(RESULT_ACCESS) ] = -1,
721 [ C(RESULT_MISS) ] = -1,
723 [ C(OP_PREFETCH) ] = {
724 [ C(RESULT_ACCESS) ] = 0x0,
725 [ C(RESULT_MISS) ] = 0x0,
728 [ C(LL ) ] = {
729 [ C(OP_READ) ] = {
730 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
731 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
733 [ C(OP_WRITE) ] = {
734 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
735 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
737 [ C(OP_PREFETCH) ] = {
738 [ C(RESULT_ACCESS) ] = 0x0,
739 [ C(RESULT_MISS) ] = 0x0,
742 [ C(DTLB) ] = {
743 [ C(OP_READ) ] = {
744 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
745 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
747 [ C(OP_WRITE) ] = {
748 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
749 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
751 [ C(OP_PREFETCH) ] = {
752 [ C(RESULT_ACCESS) ] = 0x0,
753 [ C(RESULT_MISS) ] = 0x0,
756 [ C(ITLB) ] = {
757 [ C(OP_READ) ] = {
758 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
759 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
761 [ C(OP_WRITE) ] = {
762 [ C(RESULT_ACCESS) ] = -1,
763 [ C(RESULT_MISS) ] = -1,
765 [ C(OP_PREFETCH) ] = {
766 [ C(RESULT_ACCESS) ] = -1,
767 [ C(RESULT_MISS) ] = -1,
770 [ C(BPU ) ] = {
771 [ C(OP_READ) ] = {
772 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
773 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
775 [ C(OP_WRITE) ] = {
776 [ C(RESULT_ACCESS) ] = -1,
777 [ C(RESULT_MISS) ] = -1,
779 [ C(OP_PREFETCH) ] = {
780 [ C(RESULT_ACCESS) ] = -1,
781 [ C(RESULT_MISS) ] = -1,
784 [ C(NODE) ] = {
785 [ C(OP_READ) ] = {
786 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
787 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
789 [ C(OP_WRITE) ] = {
790 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
791 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
793 [ C(OP_PREFETCH) ] = {
794 [ C(RESULT_ACCESS) ] = 0x0,
795 [ C(RESULT_MISS) ] = 0x0,
805 [ C(LL ) ] = {
806 [ C(OP_READ) ] = {
807 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
809 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
812 [ C(OP_WRITE) ] = {
813 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
815 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
818 [ C(OP_PREFETCH) ] = {
819 [ C(RESULT_ACCESS) ] = 0x0,
820 [ C(RESULT_MISS) ] = 0x0,
823 [ C(NODE) ] = {
824 [ C(OP_READ) ] = {
825 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
828 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
832 [ C(OP_WRITE) ] = {
833 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
836 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
840 [ C(OP_PREFETCH) ] = {
841 [ C(RESULT_ACCESS) ] = 0x0,
842 [ C(RESULT_MISS) ] = 0x0,
852 [ C(L1D) ] = {
853 [ C(OP_READ) ] = {
854 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
855 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
857 [ C(OP_WRITE) ] = {
858 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
859 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
861 [ C(OP_PREFETCH) ] = {
862 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
863 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
866 [ C(L1I ) ] = {
867 [ C(OP_READ) ] = {
868 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
869 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
871 [ C(OP_WRITE) ] = {
872 [ C(RESULT_ACCESS) ] = -1,
873 [ C(RESULT_MISS) ] = -1,
875 [ C(OP_PREFETCH) ] = {
876 [ C(RESULT_ACCESS) ] = 0x0,
877 [ C(RESULT_MISS) ] = 0x0,
880 [ C(LL ) ] = {
881 [ C(OP_READ) ] = {
883 [ C(RESULT_ACCESS) ] = 0x01b7,
885 [ C(RESULT_MISS) ] = 0x01b7,
891 [ C(OP_WRITE) ] = {
893 [ C(RESULT_ACCESS) ] = 0x01b7,
895 [ C(RESULT_MISS) ] = 0x01b7,
897 [ C(OP_PREFETCH) ] = {
899 [ C(RESULT_ACCESS) ] = 0x01b7,
901 [ C(RESULT_MISS) ] = 0x01b7,
904 [ C(DTLB) ] = {
905 [ C(OP_READ) ] = {
906 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
907 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
909 [ C(OP_WRITE) ] = {
910 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
911 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
913 [ C(OP_PREFETCH) ] = {
914 [ C(RESULT_ACCESS) ] = 0x0,
915 [ C(RESULT_MISS) ] = 0x0,
918 [ C(ITLB) ] = {
919 [ C(OP_READ) ] = {
920 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
921 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
923 [ C(OP_WRITE) ] = {
924 [ C(RESULT_ACCESS) ] = -1,
925 [ C(RESULT_MISS) ] = -1,
927 [ C(OP_PREFETCH) ] = {
928 [ C(RESULT_ACCESS) ] = -1,
929 [ C(RESULT_MISS) ] = -1,
932 [ C(BPU ) ] = {
933 [ C(OP_READ) ] = {
934 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
935 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
937 [ C(OP_WRITE) ] = {
938 [ C(RESULT_ACCESS) ] = -1,
939 [ C(RESULT_MISS) ] = -1,
941 [ C(OP_PREFETCH) ] = {
942 [ C(RESULT_ACCESS) ] = -1,
943 [ C(RESULT_MISS) ] = -1,
946 [ C(NODE) ] = {
947 [ C(OP_READ) ] = {
948 [ C(RESULT_ACCESS) ] = 0x01b7,
949 [ C(RESULT_MISS) ] = 0x01b7,
951 [ C(OP_WRITE) ] = {
952 [ C(RESULT_ACCESS) ] = 0x01b7,
953 [ C(RESULT_MISS) ] = 0x01b7,
955 [ C(OP_PREFETCH) ] = {
956 [ C(RESULT_ACCESS) ] = 0x01b7,
957 [ C(RESULT_MISS) ] = 0x01b7,
1000 [ C(LL ) ] = {
1001 [ C(OP_READ) ] = {
1002 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1003 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1005 [ C(OP_WRITE) ] = {
1006 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1007 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1009 [ C(OP_PREFETCH) ] = {
1010 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1011 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1014 [ C(NODE) ] = {
1015 [ C(OP_READ) ] = {
1016 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1017 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1019 [ C(OP_WRITE) ] = {
1020 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1021 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1023 [ C(OP_PREFETCH) ] = {
1024 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1025 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1035 [ C(L1D) ] = {
1036 [ C(OP_READ) ] = {
1037 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1038 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1040 [ C(OP_WRITE) ] = {
1041 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1042 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1044 [ C(OP_PREFETCH) ] = {
1045 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1046 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1049 [ C(L1I ) ] = {
1050 [ C(OP_READ) ] = {
1051 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1052 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1054 [ C(OP_WRITE) ] = {
1055 [ C(RESULT_ACCESS) ] = -1,
1056 [ C(RESULT_MISS) ] = -1,
1058 [ C(OP_PREFETCH) ] = {
1059 [ C(RESULT_ACCESS) ] = 0x0,
1060 [ C(RESULT_MISS) ] = 0x0,
1063 [ C(LL ) ] = {
1064 [ C(OP_READ) ] = {
1066 [ C(RESULT_ACCESS) ] = 0x01b7,
1068 [ C(RESULT_MISS) ] = 0x01b7,
1074 [ C(OP_WRITE) ] = {
1076 [ C(RESULT_ACCESS) ] = 0x01b7,
1078 [ C(RESULT_MISS) ] = 0x01b7,
1080 [ C(OP_PREFETCH) ] = {
1082 [ C(RESULT_ACCESS) ] = 0x01b7,
1084 [ C(RESULT_MISS) ] = 0x01b7,
1087 [ C(DTLB) ] = {
1088 [ C(OP_READ) ] = {
1089 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1090 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1092 [ C(OP_WRITE) ] = {
1093 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1094 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1096 [ C(OP_PREFETCH) ] = {
1097 [ C(RESULT_ACCESS) ] = 0x0,
1098 [ C(RESULT_MISS) ] = 0x0,
1101 [ C(ITLB) ] = {
1102 [ C(OP_READ) ] = {
1103 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1104 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1106 [ C(OP_WRITE) ] = {
1107 [ C(RESULT_ACCESS) ] = -1,
1108 [ C(RESULT_MISS) ] = -1,
1110 [ C(OP_PREFETCH) ] = {
1111 [ C(RESULT_ACCESS) ] = -1,
1112 [ C(RESULT_MISS) ] = -1,
1115 [ C(BPU ) ] = {
1116 [ C(OP_READ) ] = {
1117 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1118 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1120 [ C(OP_WRITE) ] = {
1121 [ C(RESULT_ACCESS) ] = -1,
1122 [ C(RESULT_MISS) ] = -1,
1124 [ C(OP_PREFETCH) ] = {
1125 [ C(RESULT_ACCESS) ] = -1,
1126 [ C(RESULT_MISS) ] = -1,
1129 [ C(NODE) ] = {
1130 [ C(OP_READ) ] = {
1131 [ C(RESULT_ACCESS) ] = 0x01b7,
1132 [ C(RESULT_MISS) ] = 0x01b7,
1134 [ C(OP_WRITE) ] = {
1135 [ C(RESULT_ACCESS) ] = 0x01b7,
1136 [ C(RESULT_MISS) ] = 0x01b7,
1138 [ C(OP_PREFETCH) ] = {
1139 [ C(RESULT_ACCESS) ] = 0x01b7,
1140 [ C(RESULT_MISS) ] = 0x01b7,
1150 [ C(L1D) ] = {
1151 [ C(OP_READ) ] = {
1152 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1153 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1155 [ C(OP_WRITE) ] = {
1156 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1157 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1159 [ C(OP_PREFETCH) ] = {
1160 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1161 [ C(RESULT_MISS) ] = 0,
1164 [ C(L1I ) ] = {
1165 [ C(OP_READ) ] = {
1166 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1167 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1169 [ C(OP_WRITE) ] = {
1170 [ C(RESULT_ACCESS) ] = -1,
1171 [ C(RESULT_MISS) ] = -1,
1173 [ C(OP_PREFETCH) ] = {
1174 [ C(RESULT_ACCESS) ] = 0,
1175 [ C(RESULT_MISS) ] = 0,
1178 [ C(LL ) ] = {
1179 [ C(OP_READ) ] = {
1180 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1181 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1183 [ C(OP_WRITE) ] = {
1184 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1185 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1187 [ C(OP_PREFETCH) ] = {
1188 [ C(RESULT_ACCESS) ] = 0,
1189 [ C(RESULT_MISS) ] = 0,
1192 [ C(DTLB) ] = {
1193 [ C(OP_READ) ] = {
1194 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1195 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1197 [ C(OP_WRITE) ] = {
1198 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1199 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1201 [ C(OP_PREFETCH) ] = {
1202 [ C(RESULT_ACCESS) ] = 0,
1203 [ C(RESULT_MISS) ] = 0,
1206 [ C(ITLB) ] = {
1207 [ C(OP_READ) ] = {
1208 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1209 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1211 [ C(OP_WRITE) ] = {
1212 [ C(RESULT_ACCESS) ] = -1,
1213 [ C(RESULT_MISS) ] = -1,
1215 [ C(OP_PREFETCH) ] = {
1216 [ C(RESULT_ACCESS) ] = -1,
1217 [ C(RESULT_MISS) ] = -1,
1220 [ C(BPU ) ] = {
1221 [ C(OP_READ) ] = {
1222 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1223 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1225 [ C(OP_WRITE) ] = {
1226 [ C(RESULT_ACCESS) ] = -1,
1227 [ C(RESULT_MISS) ] = -1,
1229 [ C(OP_PREFETCH) ] = {
1230 [ C(RESULT_ACCESS) ] = -1,
1231 [ C(RESULT_MISS) ] = -1,
1241 [ C(L1D) ] = {
1242 [ C(OP_READ) ] = {
1243 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1244 [ C(RESULT_MISS) ] = 0,
1246 [ C(OP_WRITE) ] = {
1247 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1248 [ C(RESULT_MISS) ] = 0,
1250 [ C(OP_PREFETCH) ] = {
1251 [ C(RESULT_ACCESS) ] = 0x0,
1252 [ C(RESULT_MISS) ] = 0,
1255 [ C(L1I ) ] = {
1256 [ C(OP_READ) ] = {
1257 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1258 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1260 [ C(OP_WRITE) ] = {
1261 [ C(RESULT_ACCESS) ] = -1,
1262 [ C(RESULT_MISS) ] = -1,
1264 [ C(OP_PREFETCH) ] = {
1265 [ C(RESULT_ACCESS) ] = 0,
1266 [ C(RESULT_MISS) ] = 0,
1269 [ C(LL ) ] = {
1270 [ C(OP_READ) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1272 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1274 [ C(OP_WRITE) ] = {
1275 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1276 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1278 [ C(OP_PREFETCH) ] = {
1279 [ C(RESULT_ACCESS) ] = 0,
1280 [ C(RESULT_MISS) ] = 0,
1283 [ C(DTLB) ] = {
1284 [ C(OP_READ) ] = {
1285 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1286 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1288 [ C(OP_WRITE) ] = {
1289 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1290 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1292 [ C(OP_PREFETCH) ] = {
1293 [ C(RESULT_ACCESS) ] = 0,
1294 [ C(RESULT_MISS) ] = 0,
1297 [ C(ITLB) ] = {
1298 [ C(OP_READ) ] = {
1299 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1300 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1302 [ C(OP_WRITE) ] = {
1303 [ C(RESULT_ACCESS) ] = -1,
1304 [ C(RESULT_MISS) ] = -1,
1306 [ C(OP_PREFETCH) ] = {
1307 [ C(RESULT_ACCESS) ] = -1,
1308 [ C(RESULT_MISS) ] = -1,
1311 [ C(BPU ) ] = {
1312 [ C(OP_READ) ] = {
1313 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1314 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1316 [ C(OP_WRITE) ] = {
1317 [ C(RESULT_ACCESS) ] = -1,
1318 [ C(RESULT_MISS) ] = -1,
1320 [ C(OP_PREFETCH) ] = {
1321 [ C(RESULT_ACCESS) ] = -1,
1322 [ C(RESULT_MISS) ] = -1,
1348 [ C(LL ) ] = {
1349 [ C(OP_READ) ] = {
1350 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1351 [ C(RESULT_MISS) ] = 0,
1353 [ C(OP_WRITE) ] = {
1354 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1355 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1357 [ C(OP_PREFETCH) ] = {
1358 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1359 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1369 [ C(L1D) ] = {
1370 [ C(OP_READ) ] = {
1371 [ C(RESULT_ACCESS) ] = 0,
1372 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1374 [ C(OP_WRITE) ] = {
1375 [ C(RESULT_ACCESS) ] = 0,
1376 [ C(RESULT_MISS) ] = 0,
1378 [ C(OP_PREFETCH) ] = {
1379 [ C(RESULT_ACCESS) ] = 0,
1380 [ C(RESULT_MISS) ] = 0,
1383 [ C(L1I ) ] = {
1384 [ C(OP_READ) ] = {
1385 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1386 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1388 [ C(OP_WRITE) ] = {
1389 [ C(RESULT_ACCESS) ] = -1,
1390 [ C(RESULT_MISS) ] = -1,
1392 [ C(OP_PREFETCH) ] = {
1393 [ C(RESULT_ACCESS) ] = 0,
1394 [ C(RESULT_MISS) ] = 0,
1397 [ C(LL ) ] = {
1398 [ C(OP_READ) ] = {
1400 [ C(RESULT_ACCESS) ] = 0x01b7,
1401 [ C(RESULT_MISS) ] = 0,
1403 [ C(OP_WRITE) ] = {
1405 [ C(RESULT_ACCESS) ] = 0x01b7,
1407 [ C(RESULT_MISS) ] = 0x01b7,
1409 [ C(OP_PREFETCH) ] = {
1411 [ C(RESULT_ACCESS) ] = 0x01b7,
1413 [ C(RESULT_MISS) ] = 0x01b7,
1416 [ C(DTLB) ] = {
1417 [ C(OP_READ) ] = {
1418 [ C(RESULT_ACCESS) ] = 0,
1419 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1421 [ C(OP_WRITE) ] = {
1422 [ C(RESULT_ACCESS) ] = 0,
1423 [ C(RESULT_MISS) ] = 0,
1425 [ C(OP_PREFETCH) ] = {
1426 [ C(RESULT_ACCESS) ] = 0,
1427 [ C(RESULT_MISS) ] = 0,
1430 [ C(ITLB) ] = {
1431 [ C(OP_READ) ] = {
1432 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1433 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1435 [ C(OP_WRITE) ] = {
1436 [ C(RESULT_ACCESS) ] = -1,
1437 [ C(RESULT_MISS) ] = -1,
1439 [ C(OP_PREFETCH) ] = {
1440 [ C(RESULT_ACCESS) ] = -1,
1441 [ C(RESULT_MISS) ] = -1,
1444 [ C(BPU ) ] = {
1445 [ C(OP_READ) ] = {
1446 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1447 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1449 [ C(OP_WRITE) ] = {
1450 [ C(RESULT_ACCESS) ] = -1,
1451 [ C(RESULT_MISS) ] = -1,
1453 [ C(OP_PREFETCH) ] = {
1454 [ C(RESULT_ACCESS) ] = -1,
1455 [ C(RESULT_MISS) ] = -1,
3448 …hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MI… in intel_pmu_init()
3511 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | in intel_pmu_init()
3513 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| in intel_pmu_init()
3515 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| in intel_pmu_init()
3517 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| in intel_pmu_init()