60 	u64				(*get_count)(u64 config);
181 static int perf_ibs_precise_event(struct perf_event *event, u64 *config)  in perf_ibs_precise_event()  argument
195 		switch (event->attr.config) {  in perf_ibs_precise_event()
197 			*config = 0;  in perf_ibs_precise_event()
202 		switch (event->attr.config) {  in perf_ibs_precise_event()
204 			*config = 0;  in perf_ibs_precise_event()
207 			*config = IBS_OP_CNT_CTL;  in perf_ibs_precise_event()
231 	u64 max_cnt, config;  in perf_ibs_init()  local
236 		config = event->attr.config;  in perf_ibs_init()
239 		ret = perf_ibs_precise_event(event, &config);  in perf_ibs_init()
250 	if (config & ~perf_ibs->config_mask)  in perf_ibs_init()
254 		if (config & perf_ibs->cnt_mask)  in perf_ibs_init()
268 		max_cnt = config & perf_ibs->cnt_mask;  in perf_ibs_init()
269 		config &= ~perf_ibs->cnt_mask;  in perf_ibs_init()
285 	hwc->config = config;  in perf_ibs_init()
302 static u64 get_ibs_fetch_count(u64 config)  in get_ibs_fetch_count()  argument
304 	return (config & IBS_FETCH_CNT) >> 12;  in get_ibs_fetch_count()
307 static u64 get_ibs_op_count(u64 config)  in get_ibs_op_count()  argument
311 	if (config & IBS_OP_VAL)  in get_ibs_op_count()
312 		count += (config & IBS_OP_MAX_CNT) << 4; /* cnt rolled over */  in get_ibs_op_count()
315 		count += (config & IBS_OP_CUR_CNT) >> 32;  in get_ibs_op_count()
322 		      u64 *config)  in perf_ibs_event_update()  argument
324 	u64 count = perf_ibs->get_count(*config);  in perf_ibs_event_update()
332 		rdmsrl(event->hw.config_base, *config);  in perf_ibs_event_update()
333 		count = perf_ibs->get_count(*config);  in perf_ibs_event_update()
338 					 struct hw_perf_event *hwc, u64 config)  in perf_ibs_enable_event()  argument
340 	wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask);  in perf_ibs_enable_event()
351 					  struct hw_perf_event *hwc, u64 config)  in perf_ibs_disable_event()  argument
353 	config &= ~perf_ibs->cnt_mask;  in perf_ibs_disable_event()
354 	wrmsrl(hwc->config_base, config);  in perf_ibs_disable_event()
355 	config &= ~perf_ibs->enable_mask;  in perf_ibs_disable_event()
356 	wrmsrl(hwc->config_base, config);  in perf_ibs_disable_event()
390 	u64 config;  in perf_ibs_stop()  local
398 	rdmsrl(hwc->config_base, config);  in perf_ibs_stop()
402 		perf_ibs_disable_event(perf_ibs, hwc, config);  in perf_ibs_stop()
414 	config &= ~perf_ibs->valid_mask;  in perf_ibs_stop()
416 	perf_ibs_event_update(perf_ibs, event, &config);  in perf_ibs_stop()
527 	u64 *buf, *config, period;  in perf_ibs_handle_irq()  local
545 	config = &ibs_data.regs[0];  in perf_ibs_handle_irq()
546 	perf_ibs_event_update(perf_ibs, event, config);  in perf_ibs_handle_irq()
602 		perf_ibs_disable_event(perf_ibs, hwc, *config);  in perf_ibs_handle_irq()