Lines Matching refs:u64

22 	u64 _val = (val);						\
58 		u64		idxmsk64;
60 	u64	code;
61 	u64	cmask;
111 	u64	bts_buffer_base;
112 	u64	bts_index;
113 	u64	bts_absolute_maximum;
114 	u64	bts_interrupt_threshold;
115 	u64	pebs_buffer_base;
116 	u64	pebs_index;
117 	u64	pebs_absolute_maximum;
118 	u64	pebs_interrupt_threshold;
119 	u64	pebs_event_reset[MAX_PEBS_EVENTS];
127 	u64                 config;	/* extra MSR config */
128 	u64                 reg;	/* extra MSR number */
192 	u64			tags[X86_PMC_IDX_MAX];
206 	u64			pebs_enabled;
216 	u64				br_sel;
221 	u64				intel_ctrl_guest_mask;
222 	u64				intel_ctrl_host_mask;
228 	u64				intel_cp_status;
247 	u64				perf_ctr_virt_mask;
422 	u64			config_mask;
423 	u64			valid_mask;
454 		u64	lbr_format:6;
455 		u64	pebs_trap:1;
456 		u64	pebs_arch_reg:1;
457 		u64	pebs_format:4;
458 		u64	smm_freeze:1;
463 		u64	full_width_write:1;
465 	u64	capabilities;
475 		u64 event:8,
491 	u64 value;
523 	u64		(*event_map)(int);
528 	u64		cntval_mask;
535 	u64		max_period;
564 	ssize_t		(*events_sysfs_show)(char *page, u64 config);
582 	u64			intel_ctrl;
606 	u64		lbr_sel_mask;		   /* LBR_SELECT valid bits */
628 	u64 lbr_from[MAX_LBR_ENTRIES];
629 	u64 lbr_to[MAX_LBR_ENTRIES];
630 	u64 lbr_info[MAX_LBR_ENTRIES];
692 extern u64 __read_mostly hw_cache_event_ids
696 extern u64 __read_mostly hw_cache_extra_regs
701 u64 x86_perf_event_update(struct perf_event *event);
737 					  u64 enable_mask)  in __x86_pmu_enable_event()
739 	u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);  in __x86_pmu_enable_event()
798 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
799 ssize_t intel_event_sysfs_show(char *page, u64 config);
847 void intel_pmu_enable_bts(u64 config);