420 	unsigned int		event;  member
429 	.event = (e),			\
437 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx)	\  argument
438 	EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
440 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \  argument
441 	EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
475 		u64 event:8,  member
517 	int		(*hw_config)(struct perf_event *event);
539 						 struct perf_event *event);
542 						 struct perf_event *event);
554 	unsigned	(*limit_period)(struct perf_event *event, unsigned l);
597 	void		(*pebs_aliases)(struct perf_event *event);
680 int x86_perf_event_set_period(struct perf_event *event);
701 u64 x86_perf_event_update(struct perf_event *event);
728 void hw_perf_lbr_event_destroy(struct perf_event *event);
730 int x86_setup_perfctr(struct perf_event *event);
732 int x86_pmu_hw_config(struct perf_event *event);
752 void x86_pmu_stop(struct perf_event *event, int flags);
754 static inline void x86_pmu_disable_event(struct perf_event *event)  in x86_pmu_disable_event()  argument
756 	struct hw_perf_event *hwc = &event->hw;  in x86_pmu_disable_event()
761 void x86_pmu_enable_event(struct perf_event *event);
798 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
818 static inline bool intel_pmu_has_bts(struct perf_event *event)  in intel_pmu_has_bts()  argument
820 	if (event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&  in intel_pmu_has_bts()
821 	    !event->attr.freq && event->hw.sample_period == 1)  in intel_pmu_has_bts()
827 int intel_pmu_save_and_restart(struct perf_event *event);
831 			  struct perf_event *event);
871 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
873 void intel_pmu_pebs_enable(struct perf_event *event);
875 void intel_pmu_pebs_disable(struct perf_event *event);
889 void intel_pmu_lbr_enable(struct perf_event *event);
891 void intel_pmu_lbr_disable(struct perf_event *event);
913 int intel_pmu_setup_lbr_filter(struct perf_event *event);