Lines Matching defs:cpu_hw_events
177 struct cpu_hw_events { struct
181 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
182 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
183 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
184 int enabled;
186 int n_events; /* the # of events in the below arrays */
187 int n_added; /* the # last events in the below arrays;
189 int n_txn; /* the # last events in the below arrays;
191 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
192 u64 tags[X86_PMC_IDX_MAX];
194 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
195 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
197 int n_excl; /* the number of exclusive events */
199 unsigned int txn_flags;
200 int is_fake;
205 struct debug_store *ds;
206 u64 pebs_enabled;
211 int lbr_users;
212 void *lbr_context;
213 struct perf_branch_stack lbr_stack;
214 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
215 struct er_account *lbr_sel;
216 u64 br_sel;
221 u64 intel_ctrl_guest_mask;
222 u64 intel_ctrl_host_mask;
223 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
228 u64 intel_cp_status;
234 struct intel_shared_regs *shared_regs;
238 struct event_constraint *constraint_list; /* in enable order */
239 struct intel_excl_cntrs *excl_cntrs;
240 int excl_thread_id; /* 0 or 1 */
245 struct amd_nb *amd_nb;
247 u64 perf_ctr_virt_mask;
249 void *kfree_on_online[X86_PERF_KFREE_MAX];