Lines Matching refs:l
476 u32 l, h; in intel_init_thermal() local
486 rdmsr(MSR_IA32_MISC_ENABLE, l, h); in intel_init_thermal()
503 if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { in intel_init_thermal()
512 rdmsr(MSR_THERM2_CTL, l, h); in intel_init_thermal()
513 if (l & MSR_THERM2_CTL_TM_SELECT) in intel_init_thermal()
515 } else if (l & MSR_IA32_MISC_ENABLE_TM2) in intel_init_thermal()
523 rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); in intel_init_thermal()
526 (l | (THERM_INT_LOW_ENABLE in intel_init_thermal()
530 l | (THERM_INT_LOW_ENABLE in intel_init_thermal()
534 l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); in intel_init_thermal()
537 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); in intel_init_thermal()
540 (l | (PACKAGE_THERM_INT_LOW_ENABLE in intel_init_thermal()
545 l | (PACKAGE_THERM_INT_LOW_ENABLE in intel_init_thermal()
550 l | (PACKAGE_THERM_INT_LOW_ENABLE in intel_init_thermal()
556 rdmsr(MSR_IA32_MISC_ENABLE, l, h); in intel_init_thermal()
557 wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); in intel_init_thermal()
560 l = apic_read(APIC_LVTTHMR); in intel_init_thermal()
561 apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); in intel_init_thermal()