228 	u32 low = 0, high = 0;  in deferred_error_interrupt_enable()  local
231 	if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))  in deferred_error_interrupt_enable()
247 	wrmsr(MSR_CU_DEF_ERR, low, high);  in deferred_error_interrupt_enable()
255 	u32 low = 0, high = 0, address = 0;  in mce_amd_feature_init()  local
272 			if (rdmsr_safe(address, &low, &high))  in mce_amd_feature_init()
275 			if (!(high & MASK_VALID_HI))  in mce_amd_feature_init()
278 			if (!(high & MASK_CNTP_HI)  ||  in mce_amd_feature_init()
279 			     (high & MASK_LOCKED_HI))  in mce_amd_feature_init()
290 			b.interrupt_capable	= lvt_interrupt_supported(bank, high);  in mce_amd_feature_init()
296 			new	= (high & MASK_LVTOFF_HI) >> 20;  in mce_amd_feature_init()
388 	u32 low = 0, high = 0, address = 0;  in amd_threshold_interrupt()  local
408 			if (rdmsr_safe(address, &low, &high))  in amd_threshold_interrupt()
411 			if (!(high & MASK_VALID_HI)) {  in amd_threshold_interrupt()
418 			if (!(high & MASK_CNTP_HI)  ||  in amd_threshold_interrupt()
419 			     (high & MASK_LOCKED_HI))  in amd_threshold_interrupt()
426 			if (high & MASK_OVERFLOW_HI)  in amd_threshold_interrupt()
433 	__log_error(bank, true, ((u64)high << 32) | low);  in amd_threshold_interrupt()
572 	u32 low, high;  in allocate_threshold_blocks()  local
578 	if (rdmsr_safe_on_cpu(cpu, address, &low, &high))  in allocate_threshold_blocks()
581 	if (!(high & MASK_VALID_HI)) {  in allocate_threshold_blocks()
588 	if (!(high & MASK_CNTP_HI)  ||  in allocate_threshold_blocks()
589 	     (high & MASK_LOCKED_HI))  in allocate_threshold_blocks()
601 	b->interrupt_capable	= lvt_interrupt_supported(bank, high);  in allocate_threshold_blocks()